^{1}

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Multilevel inverter (MLI) is one of the most efficient power converters which are especially suited for high power applications with reduced harmonics. MLI not only achieves high output power and is also used in renewable energy sources such as photovoltaic, wind and fuel cells. Among various topologies of MLI, this paper mainly focuses on cascaded MLI with three unequal DC sources called asymmetric cascaded MLI which reduces the number of power switches. Various modulation techniques are also reviewed in literature [1] . In this paper we focus on sinusoidal (or) multicarrier pulse width modulation (SPWM) which improves the output voltage at lower modulation index for obtaining lower Total Harmonic Distortion (THD) level. The gating signal for the 13-level hybrid inverter using SPWM technique is generated using Field Programmable Gate Array (FPGA) processor. The proposed modulation technique results in reduced percentage of THD, but lower order harmonics are not eliminated. So a new technique called Selective Harmonic Elimination (SHE) is also implemented in order to reduce the lower order harmonics. The optimum switching angles are determined for obtaining minimum THD. The performance evaluation of the proposed PWM inverter is verified using an experimental model of 13-level cascaded hybrid MLI and compared with MATLAB/SIMULINK model.

In recent years multilevel inverter [

Normally a CMLI requires “n” dc sources for (2n + 1) level. But it is difficult to use separate DC sources for many applications since it requires many long cables and could lead to voltage imbalance among the DC sources.

If the number of levels is increased it results in increase in number of H-bridges.

In general the output phase voltage is given by

It can also be determined from the individual cells switching states.

It is represented as

The maximum output voltage

By closing and opening of the switches alternatively the output of H1 is obtained as

Hence _{dc}, −V_{dc}, −1/2V_{dc}, 0, +1/2V_{dc}, +V_{dc}, +3/2V_{dc} for the above CMLI. _{dc}, −3/2V_{dc}, −V_{dc}, −1/2V_{dc}, 0, +1/2V_{dc}, +V_{dc}, +3/2V_{dc}, +5/2V_{dc}.

The major advantages of ACMLI are

Less Number of dc sources;

Low switching losses;

Output switching frequencies are low;

Cost and complexity are reduced ;

Reduced harmonics level;

Increased output efficiency.

The three main modulation techniques: Fundamental frequency switching, space vector modulation (SVM), sinusoidal (or) multi carrier PWM (SPWM). In frequency switching modulation, initially the switching angles are calculated and then it is transferred to the digital system. This technique will eliminate the lower order harmonics to reduce distortion in output voltage. SVM is used to obtain the commutation state for the switches. If the number of levels in the inverter is increased this method becomes more complex. In SPWM it has several carrier signals keeping only one modulating signal. The carrier signals are triangular one and have same frequency and peak to peak amplitude so that the bands they occupy are contiguous i.e. one carrier signal will have a contact with other signal. The modulating signal is pure sinusoidal and at every instant each carrier signal is compared with modulating signal. In each comparison if the modulating signal is greater than the carrier signal it gives one or otherwise zero. The results are added to give the voltage level, which is required at the output terminal of the inverter. SPWM is further categorized in to 2 groups namely carrier disposition (CD) and phase disposition (PD) method. To sample the reference waveform in CD method, the number of carrier signals is displaced by contiguous increment in amplitude of the reference waveform. Similarly the multi carrier phase is shifted in case of PD method. The phase disposition method is implemented here in this paper as it gives least THD.

Since explained in the earlier methods of CMLIs, it is necessary to implement a new design to overcome the

disadvantages of the other methods. So a new design of topology is required to form an asymmetric inverter as shown in

The new topology comprises a Spartan 3E FPGA processor with a control of modulation index level to form various levels of inverter. The basic operation of FPGA processor is explained in chapter 6. Three Flywheel diodes are used to prevent the back emf from triggering and other circuits in the proposed model. By using FPGA the gating signal for 13-level inverter is generated for employing the SPWM technique. The hardware prototype model is also shown in

To produce a 13-level output the proposed modulation technique carries six carrier signals with one modulating signal. The carrier waveform for the proposed system is shown in

S5 | S6 | S7 | S1 | S2 | S3 | S4 | Output voltage V_{d} |
---|---|---|---|---|---|---|---|

0 | 0 | 1 | 1 | 0 | 1 | 0 | +V_{d} |

0 | 1 | 1 | 1 | 0 | 1 | 0 | +V_{d}/6 |

0 | 1 | 1 | 1 | 0 | 1 | 0 | +V_{d}/3 |

1 | 0 | 0 | 1 | 0 | 1 | 0 | +3V_{d}/6 |

1 | 0 | 1 | 1 | 0 | 1 | 0 | +2V_{d}/3 |

1 | 1 | 1 | 1 | 0 | 1 | 0 | +4V_{d}/5 |

0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |

0 | 0 | 1 | 0 | 1 | 0 | 1 | −V_{d} |

0 | 1 | 1 | 0 | 1 | 0 | 1 | −V_{d}/6 |

0 | 1 | 1 | 0 | 1 | 0 | 1 | −V_{d}/3 |

1 | 0 | 0 | 0 | 1 | 0 | 1 | −3V_{d}/6 |

1 | 0 | 1 | 0 | 1 | 0 | 1 | −2V_{d}/3 |

1 | 1 | 1 | 0 | 1 | 0 | 1 | −4V_{d}/5 |

The simulation model for a 13-level inverter with R load is shown in

that the odd harmonics of 3^{rd}, 5^{th}, 7^{th}, and 9^{th} harmonic levels are most dominant. Hence a new method of SHEPWM is suggested for minimizing such kind of odd harmonics.

SHE is commonly adopted in medium and high power inverter applications where the switching frequency is low enough to minimize the switching losses. The effectiveness of this method is fully depends on switching angles. So, for determining the optimum switching angles several algorithms have been developed. Usually it is done using optimization techniques such as Newton Raphson method [

1) The switching angles are too calculated through a set of non-linear and transcendental equations.

2) The determined switching angles are to be stored in look up table (LUT) for real time applications.

In order to implement this in real time power electronic applications [

In this paper for finding the values of switching angles the Newton Raphson method has been implemented which has a set of solutions to reduce the lower order harmonics. The main advantages of this SHE is to obtain lower order harmonics at the output side. If the inverter wants to supply AC power to an AC load with constant frequency a filter is usually installed in its output side. In this method when the lower order harmonics are eliminated the output will have only higher order harmonics and it should be attenuated by the filter. Hence the cut-off frequency will be increased which will results in filter size.

Solution for SHE Modulation

The output for 13-level inverter and the Fourier series can be expressed as

The actual waveform consists of sine terms only.

The even harmonics are absent thus

Thus the above equation is reduced to

where

From the above equation the fundamental output equation can be expressed as

As shown in

The modulation index is given by

As explained earlier, the main objective of this paper is to generate the output with the ability to eliminate the 3^{rd}, 5^{th}, 7^{th}, 9^{th} and 11^{th} order harmonics. So in order to obtain the switching angles the following transcendental equations are solved.

Since it is difficult to solve the above equations analytically a different approach called Newton Raphson method is implemented to find the switching angles. The switching angles are then examined for their corresponding THD and is given by

where ^{th }harmonic component and ^{rd}, 5^{th}, 7^{th}, and 9^{th} harmonics are minimized by varying the modulation index from 0 to 1. For the modulation index 0.85,

the switching angles are 0.62, 23.10, 44.42, 54.37 and 63.57 the THD is 8.59%. If the modulation index is 0.97 the various switching angles are 4.82, 12.69, 23.32, 24.46, 37.27 and THD is around 6.19% which highly satisfies the IEEE 519-1992 harmonic guidelines. Thus if the modulation index has been increased the % THD would be reduced.

The simulated output result using MATLAB/ SIMULINK model is verified with an experimental prototype hybrid cascaded multilevel inverter. The experimental setup of the proposed 13-level hybrid cascaded multilevel inverter model is shown in

The output result of the experimental setup is shown in

The PWM waveform is produced by a ramping signal with a consistent level of DC source. The FPGA is designed specially by considering the needs of cost sensitive and high volume of electronic applications. The Spartan-3E processor has increased amount of logic per I/O then the earlier version and so the cost per logic cell is reduced. Hence the performance of the system is improved. Spartan-3E is ideally suited for wider range of consumer electronics including home networking, digital television, display/ projection and broadband access. The experimental results are compared with the matlab output and found that both the results are almost equal in amplitude and the level of THD which could meet the IEEE 519-1992 harmonic guidelines. The simulation result thus obtained by RL type load is ac current near sinusoidal output with p.f of 0.9 and THD is 1.09% which is shown in

The proposed topology of 13-level ACHMLI is experimentally verified with the satisfied results of MATLAB/ SIMULINK model. This topology is also simulated by using SHEPWM technique for minimizing the most dominant odd harmonics. The ratio (1:2:4) of the DC source voltage and the firing angle computation has performed to obtain a minimum THD value of the load voltage and current. Here the realization of the modulation index is also observed for maintaining the AC output voltage by varying the modulation index between 0 ˂ m ≤ 1.

This method shows that there is no power flow from load to any of the inverter cell. Hence the regeneration of power is avoided during the normal operating condition. From the above analysis by the comparison of output results, it is realized that the proposed model resulted lower THD level which could meet the IEEE 519-1992 standard. Also this can be used for any non-linear loads and solar photovoltaic application etc. Further the investigation is extended for PV applications by minimizing the switching losses with suitable DC converter and to find out the most suitable method for optimizing the lowest THD level.

Natesan Sivakumar,S. Sumathi, (2016) Reduction of THD in Thirteen-Level Hybrid PV Inverter with Less Number of Switches. Circuits and Systems,07,3403-3414. doi: 10.4236/cs.2016.710290