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This work presents an implementation of an innovative single phase multilevel inverter using capacitors with reduced switches. The proposed Capacitor pattern H-bridge Multilevel Inverter (CPHMLI) topology consists of a proper number of Capacitor connected with switches and power sources. The advanced switching control supplied by Pulse Width Modulation (PDPWM) to attain mixed staircase switching state. The charging and discharging mode are achieved by calculating the voltage error at the load. Furthermore, to accomplish the higher voltage levels at the output with less number of semiconductors switches and simple commutation designed using CPHMLI topology. To prove the performance and effectiveness of the proposed approach, a set of experiments performed under various load conditions using MATLAB tool.

In recent years, the amount of power equipment is increasing rapidly. Nowadays, multilevel converters have been increasingly used in high-power medium-voltage drive applications. Multilevel Inverter (MLI) has a distinctive arrangement that allows reaching high voltage and power levels without the use of transformers. They are specially suited for applications like renewable energy systems, electric vehicles (EVs) and other innovative power electronic utilities in medium and high power applications which need low THD. There are three types of multilevel inverters: diode clamped, flying capacitors, and cascaded H-bridge multilevel inverter which are mainly based on symmetric and asymmetric value of dc power supplies. Although each topology has its own advantages, drawbacks of each topology limit their applications. Although these converters have a lot of advantages over the classic inverters, using aforementioned conventional topologies needs more number of required power switches, power supplies and large capacitor banks. Furthermore voltage of the capacitors tends to be discharged theoretically and therefore charge balancing control processing is necessary.

Cascaded Multilevel Inverters (CMLI) are formed by the series connection of two or more single-phase H- bridge inverters. The multilevel converters which gained popularity in high power applications due to their low switch leg voltage stress and modularity. CMLI introduces the idea of using separate DC sources to produce an AC voltage waveform. Each H-bridge inverter is connected to its own DC source Vdc. By cascading the AC outputs of each H-bridge inverter, an AC voltage waveform is produced. The proposed converters can generate staircase voltage waveform at the output with high quality and desired spectrum. The desired output voltage is synthesized by appropriate switching of several dc voltage links which leads to decrease voltage stresses on switches and total harmonic distortion than previous multilevel converters.

Numerous related research works are already existed in literature which based on multilevel converter of the system. Some of them are reviewed here.

The conventional types of MLI configurations using reviews are discussed. The multilevel inverters are categorized into diode clamped (DCMLI) [

Although in [

Nowadays, many researchers have presented numerous developed structures of MLIs with less number of key components such as number of required switches, gate drivers, power supplies and so on discussed [

The duty cycle of dc bus capacitors for FCMLIs by using the existing redundancy switching states (RSSs) [

Level phase-shift modulation approach [

The distinctive features of these types of inverters are that they can increase the flexibility of systems by switching between several capacitors in series or parallel modes and therefore can transfer more input power to the output. A new family of cascade and hybrid SCISPC [

The output voltage of a power inverter is to be a pure sinusoidal waveform with minimum distortion. But for the practical inverters, the output voltage is a series of rectangular waveforms. The major issues for the control of the power inverters are to get suitable modulation methods and to control the output rectangular waveforms to synthesize the desired waveforms. Therefore, a modulation control method is required to get a desired output voltage level and to eliminate higher order harmonics as much as possible. Hence the proposed method focussed on new cascaded H-bridge multilevel inverter topology with various modulation techniques has been discussed.

Now by considering the proposed structure (

The Capacitor pattern H-bridge Multilevel Inverter (CPHMLI) based modulation algorithm proposed to remove the voltage oscillation for variable phase inverter circuits. The main aim is to reduce the number of switching commutations to have total control over the voltage swings. The amplitude of the low-frequency switching voltage oscillations increases under certain nonlinear loads. So that the situation causes the system becomes unstable due to voltage variations. The proposed topology based control strategies able to control the switching voltage oscillations than previous converters and n-level diode-clamped converters.

This work belongs to contribute the following features based on advanced modulation control strategy. The proposed inverter topology ultimately controls the voltage, thus removing the low-frequency switching voltage oscillations of multiphase converters under any unbalanced and nonlinear loads. The proposed PDPWM approach eliminates the sophisticated vector diagrams analysis with many vectors when the number of phases increases. Hence, the algorithm used as a recursive method that makes it extensible to n-phase converters in future. Additionally, it adds the new features of directly controlled closed-loop algorithm that does not involve any linear controllers.

The controller monitors the level of input voltage V_{in} at each duty cycle and triggers one of the switch to flow

the input voltage and this makes set of capacitors to be charged with the help of diode conduction state. By reading the input voltage V_{in}, the controller estimates the switching loss and choose the optimal circuit to be triggered based on the voltage value present in the capacitors present in the selected circuit. The controller maintains number of possible circuits as patterns and for each of the pattern the controller computes the possible output voltage V_{out}. Based on the output voltage could be generated a single switch is selected and the circuit is triggered to conduct the voltage and produce efficient output voltage.

In this work, the number of required capacitors in each of proposed CPHMLI units is optimized from the view point of maximum produced output voltage levels for proposed CPHMLI with minimum number of IGBTs. This optimization is done based on asymmetric value of dc sources according to Equation (1). In general, the number of output voltage levels for proposed CPHMLI is obtained by:

where N Sublevels is the number of output voltage levels for proposed CPHMLI which is calculated by Equation (2). Then equation of (1) can be rewritten as:

On the other hand, the relation of in terms of (number of required IGBTs for proposed CSMLI) and is equalized to Equation (2): N_{IGBT} and m as

Also with inserting Equation (1) into Equation (3) and Equation (2):

In order to obtain the optimal number of capacitor from each of CPHMLIs, the variation of against for specific number of N_{IGBT}.

In this case, all of the switches are driven by fundamental switching frequency whereas the sinusoidal reference voltage is compared with some available dc voltage levels and create the related gate switching pulses. The most advantage of this switching method is referred to low switching frequency which yields to reduction of switching loss. Details of fundamental switching modulation strategy are not objective of this paper.

In addition from

Thus, the maximum discharging amount of each capacitor can be defined as Equation (5) in one half cycles:

where, T is the period of one cycle, f_{s} is the frequency of output voltage and I is the amplitude of load current, respectively. On the other hand, in proposed 17-level inverter, this time interval varies for T_{s} based on longest discharging cycle (LDC) of each capacitors. According to

Thus, with considering the as maximum allowable voltage ripple, the optimum value of capacitors by

Switching states | ON Switches | V_{0} | C_{1} | C_{2} |
---|---|---|---|---|

1 | 4V_{dc} + V_{c}_{,1} + V_{c}_{,2} | D | D | |

2 | 4V_{dc} + V_{c}_{,2} | C | D | |

3 | 3V_{dc} + V_{c}_{,2} | C | D | |

4 | 4V_{dc} + V_{c}_{,1} | D | C | |

5 | 4V_{dc} | C | C | |

6 | 3V_{dc} | C | C | |

7 | V_{dc} + V_{c}_{,1} | D | C | |

8 | V_{dc} | C | C | |

9 | 0 | C | C | |

10 | −V_{dc} | C | C | |

11 | −V_{dc} − V_{c}_{,1} | D | C | |

12 | −3V_{dc} | C | C | |

13 | −4V_{dc} | C | C | |

14 | −4V_{dc} − V_{c,1} | D | C | |

15 | −3V_{dc} − V_{c,2} | C | D | |

16 | −4V_{dc} − V_{c}_{,2} | C | D | |

17 | −4V_{dc} − V_{c}_{,1} − V_{c}_{,2} | D | D |

The proper duty cycle selected using capacitor pattern based pulse triggering for the proposed inverter topology. The pattern is generated based on the duty cycle according to the switch being triggered, the method identifies set of patterns which are triggered to get charged and set of capacitors gets discharged. The pattern generator identifies the capacitors at each pattern which gets charged at the specific selection of switch and their new voltage value will be updated to the pattern set.

The proposed capacitor pattern based hybrid multilevel inverter has been implemented and simulated using Matlab. The THD and efficiency of the proposed CPHMLI has been evaluated with number of duty cycles and has produced efficient Staircase output voltage.

multilevel inverter and proposed CPHMLI topology. The proposed topology requires very less number of IGBT switches, Diodes, capacitors and dc input voltage than the other methods. Therefore the proposed CPHMLI topology consists of ten switches, two diodes, two input dc voltage source and two capacitors to achieve 17 level step output voltage.

From the simulink environment FFT analyzer evaluates the different THD for various values of modulation Index ma. These evaluated values for different modulation techniques are listed in

From Graph 1, it is clear that the proposed CPHMLI inverter has Less Total harmonic distortion for various modulation index values such as M = 1, 0.8, 0.6, 0.4 than the others proposed earlier.

Graph 2 shows that the proposed method has more efficiency compare to other two methodologies for 17-level cascaded H-bridge multilevel inverter topology and the same input values. Hence the proposed topology provides the low harmonics of 8.5% and higher efficiency of 95% for medium voltage high power applications.

This work proposed a novel schematic design and circuit for Capacitor pattern H-bridge Multilevel Inverter (CPHMLI) topology to reduce the distortions in output voltage. The proposed capacitor pattern based H-bridge Multilevel Inverter topology design in photovoltaic system was simulated with MATLAB/SIMULINK software. The proposed model reduces the required components and harmonic losses with the help of maintaining various

Graph 1. Performance comparison of THD for various Modulation index.

Sl. No. | Parameters | MLI | CASCADED H-BRIDGE MLI (CHMLI) | CAPACITOR PATTERN BASED CASCADED H-BRIDGE MLI(CPHMLI) |
---|---|---|---|---|

1 | N_{IGBT} | 12 | 12 | 10 |

2 | N_{diode} | 2 | 2 | 2 |

3 | N_{Capacitor} = N_{dc} | 2 | 2 | 2 |

4 | V_{block} | 20V_{dc} | 24V_{dc} | 20V_{dc} |

5 | N_{Currentpath,max} | 6 | 6 | 5 |

Step Level | Modulation Techniques used | THD (%) | |||
---|---|---|---|---|---|

m_{a} = 1.0 | m_{a} = 0.8 | m_{a} = 0.6 | m_{a} = 0.4 | ||

17 | SPWM | 12.71 | 16.13 | 20.08 | 30.83 |

17 | SVPWM | 13.44 | 15.91 | 19.78 | 30.2 |

17 | Capacitor Pattern based Phase Diposition PWM (PDPWM) | 12.05 | 15.08 | 19.4 | 26.48 |

Sl. No. | Step Level | Modulation Techniques used | THD (%) | Output Power Efficiency (%) |
---|---|---|---|---|

1 | 17 | Fundamental switching frequency control (FSFC) | 26 | 87 |

2 | 17 | SPWM | 17 | 89 |

3 | 17 | SVPWM | 15 | 92 |

4 | 17 | Capacitor Pattern based Phase Diposition PWM (PDPWM) | 8.5 | 95 |

Graph 2. Comparison of different CHMLI system.

capacitor patterns which are discharged and list of capacitors which are gets charged at each duty cycle and at each switch condition. At each duty cycle the controller identifies the capacitors being charged and discharged according to the switch conditions. Also, the controller performs voltage approximation to identify the output voltage for each pattern. The proposed design reduces the voltage oscillations by adapting the capacitor as auxiliary circuit. The proposed schematic is hard wired to evaluate the performance and has produced efficient results. The proposed design has produced very good results and the output voltage and current produced are high. The efficiency produced by the design has been evaluated as 95% with low THD of 8.5% which is a successful output. The proposed design could be further improved by adapting more strategic voltage control algorithms and designs.

M. S. Saravanan,R. Jeyabharath, (2016) Capacitor Pattern H-Bridge Multilevel Inverter (CPHMLI) Using Phase Diposition Pulse Width Modulation for Grid Applications. Circuits and Systems,07,3310-3319. doi: 10.4236/cs.2016.710282