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Orthogonal frequency-division multiplexing (OFDM) is a multi carrier modulation scheme mainly used for digital communications. The performance of OFDM system heavily depends on the synchronization scheme used. In most cases, the accuracy level of synchronization will be worsened by the error caused in fixed point arithmetic involved. In this paper, we analyze the impact of the fixed point arithmetic on the performance of the coarse timing and frequency synchronization. Here with an analytical approach through numerical simulations bit length of IEEE 754 standard single precision format is optimized according to the required degree of accuracy for low complexity. Also, a complete precision level requirement for FFT computations with all possible modulation types is obtained. The proposed precision model is compared with IEEE standard single precision model and its efficiency in OFDM synchronization process is proved through MATLAB simulations. Finally, the complexity reduction of proposed precision model in both addition and subtraction is proved against single precision format using hardware synthesis. Here we proved that more than 50% complexity reduction is achieved as compared to standard precision models without compromising quality. The quality retention of proposed model is proved in both timing and frequency synchronization process.

In recent years, floating-point computation has major impact in applications like industrial automation, imaging processing, and signal computing where high dynamic range is an essential. But due to arithmetic complexity of using floating-point computation still fixed-point computation is more common in many applications. FFT is an efficient computation of the DFT, which provides a sampled Fourier Transform, for discrete-time finite length sequences.

Though FFT is extensively used to analyze the signal characteristics, it is now a basic building block in any broadband wireless communications used for sub carrier mapping. OFDM is the most prominent method in any wireless standards because of its robustness against linear time variant channel conditions. OFDM is robust against multipath fading still it has some significant challenges due to its sensitiveness to synchronization errors; it makes the task of estimating these errors for proper synchronization. In many papers, they were used pre defined binary sequences for correcting both timing and frequency offsets P. H. Moose, J.-J. van de Beek and H. Minn et al. [^{−16} to 2^{16} with considerable quantization error during FFT computations.

This paper starts by introducing synchronization process in OFDM. The effect of arithmetic computation in synchronization and also provides reasons why high precision and low complexity are desirable.

The baseband modulated signal of OFDM systems is transmitted across various sub bands by frequency hopping. A symbol is a concatenation of IFFT output of samples plus CP. Dedicated preambles are used for timing synchronization, carrier frequency offset recovery and channel estimation. The 802.11a standard M. Ghogho et al. [

Timing synchronization is achieved by using a training sequence whose first half is equal to its second half in the time domain. In receiver side both auto correlation in Equation (1) and cross-correlation in Equation (2) techniques are used for fine time synchronization as shown in

magnitude is very sensitive to AWGN and multi-path channels, which makes the estimation over a threshold difficult.

where * is the convolution operator, yrLTS is the received sequence and y(n) is the output.

where L is the length of the cross-correlation.

Since OFDM system is very sensitive to frequency offset, high precision in frequency offset estimation and compensation is important Zoran Cvetkovic et al. [

During the course of an FFT computation it is well known that to avoid loss of dynamic range, numerical issues much be dealt with at each butterfly computation stage, leading to a variety of tradeoffs. For example in many cases 32 bits are used to represent complex symbols to avoid loss of coverage during IFFT computations on transmitter side. In best case maximum constellation order used is 64-QAM with maximum possible FFT length will be 2048 point.

Fixed point design was based on following parameters:

・ Dynamic range of each signal involved.

・ Minimum number of bits required for it.

・ Robustness analyzes by performing BER simulations.

In real time processing to minimize hardware resources, the word length is kept same by rounding results after appropriate groups of operations, but in this case dynamic range would suffer. Alternatively, word lengths could grow a fixed number of bits after each arithmetic operation to accommodate final results. Here through exhaustive MATLAB simulations dynamic ranges of all modulation types are calculated and showed in

Modulation type | Maximum constellation output | Maximum possible value from 2018 FFT |
---|---|---|

BPSK (2) | 1 + 0j or 0 + 1j | 2048 |

QPSK (4) | 1 + 1j | 2.048e+ 003 + 2.048e + 003j |

16-QAM (16) | 3 + 3j | 6.144e + 003 + 6.144e + 003j |

64-QAM (64) | 7 + 7j | 1.4336e + 004 + 1.4336e + 004j |

In recent years many papers have been published on the effect of time and frequency offset on the performance of an OFDM system, as in F. Tufvesson, E. G. Larsson et al. [

However, in fixed point truncation of LSB part to keep output bit width as constant leads rounding error and fraction numbers are not represented cause quantization error. It leads to some considerable degradation in signal precision. Many error compensation algorithms have been proposed still all are insufficient when quality is demanded. In any OFDM system synchronization is done by sending some identical training symbols repeatedly. In receiver side cross correlator uses these training symbols as a known reference signal and the timing and frequency offset can be easily estimated using log-likelihood function Michele Morelli et al. [

Low-power and area efficient on-chip design models only preferred. High accuracy precision model is required for accurate estimation channels time varying nature. By considering all these factors into account, here we proposed an effective implementation of the synchronization algorithms with least precision FP model. Here word length optimization is performed in standard FP computations to improve the design performance with reduced complexity.

In FP arithmetic dynamic range is determined by exponent bit-width. We found the maximum possible dynamic range of various modulation types with 2048 point FFT in

On the other hand, the accuracy of FFT is not degraded when narrowing the bit-width of exponent and mantissa. The influence of decreasing bit-width on standard IEEE single precision 32-bit floating point will lead the way to use floating point arithmetic based FFT computations in all wireless applications. In order to find the basic exponent bit-width required to cover the values given in

In this section, the performance of proposed model is compared with fixed point and high precision model by simulating it on MATLAB platform. In our simulation, 64 sub-carriers, 16-QAM modulation are used, CP is chosen as N/4 N, the simulation is based on AWGN channel, and for synchronization standard 802.11a preamble is used.

From

However, the performance degradation of fixed point model will always be greater than timing synchronization process because of its FFT computation on receiver side. Due to stage wise computation of FFT error caused at one stage will propagate through all other remaining stages leads severe performance degradation during channel estimation process. Therefore, the performance loss of fixed point FFT computation should be taken into account when frequency offset is computed. In our proposed customized model there is no performance loss during FFT computation as it can cover all dynamic ranges as we discussed earlier (

From

The complexity of the synchronization scheme largely depends on bit-width used to represent the symbols. In this paper, we compare our proposed precision model with high precision for complexity reduction. The proposed architecture is modeled using the Verilog HDL and synthesized using ALTERA Cyclone III EP3C16F484C6 device. Detailed area results are shown in ^{rd} for addition and multiplication respectively as compared to single precision model. The design saves more area in time synchronization since large number of addition and multiplications are used in correlators.

Here we proved the bit reduction efficiency of floating point computation and its robustness against computa-

Customized FP | Sign | Exponent | Mantissa | Min | Max |
---|---|---|---|---|---|

16 bit | 1 bit | 5 bit | 10 bit | 2.9802e−08 | 6.5536e+04 |

Logic utilization | Single precision | Fixed point | Customized floating point |
---|---|---|---|

Logical elements | 347 | 49 | 154 |

Logic utilization | Single precision | Fixed point | customized floating point |
---|---|---|---|

Logical elements | 97 | 49 | 27 |

9-bit embedded multiplier | 7 | 2 | 2 |

tional errors. The OFDM system is very sensitive to frequency offset, high precision in frequency offset com- putation is important for an accurate compensation. The proposed precision can cover all dynamic ranges and its efficiency and complexity over full precision model is verified. The results show that the developed customized floating point based OFDM can consume very less number of resources to provide cost effective and high performance solution as compared to single precision models for wireless communication applications. It is also observed that there is no performance gab between full precision and proposed precision model in both time and frequency synchronization. To extend this proposed model for low complexity, one can reduce the mantissa bit sizes by compromising the precision level of OFDM system model.

The author gratefully acknowledges the support provided by his supervisor Dr. M. Kannan, Mr. D. Rajaram and thank the management of Apollo Engineering College for encouraging the research work.

V. Janakiraman,M. Kannan, (2016) Performance Analysis of OFDM Synchronization Using Customized Floating Point for Low Complexity. Circuits and Systems,07,3112-3120. doi: 10.4236/cs.2016.710264