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This paper proposes the design and experimentation of digital control of soft-switched interleaved boost converter using FPGA for Telecommunication System. The switching devices in the proposed converter are turned on and off with Zero Voltage Switching (ZVS) and Zero Current Switching (ZCS) respectively. The circuit is operated in Continuous Conduction Mode (CCM) with various load ranges having duty cycle of more than 50%. The proposed converter is studied by developing the simulation module in MATLAB/SIMULINK. A PI controller is designed and implemented in FPGA to obtain a regulated DC output for line and load variations. Simulation and experimentation results are verified with a prototype development of the proposed converter. The results indicate that the converter performance is enhanced with closed loop control.

This paper is unique which develops digital pulse-width-modulation (DPWM) control of soft switching boost power converter. A target application is FPGA-based voltage regulation of the power converter against supply voltage variations and load variations. A wide-ranging of framework for load-line control is developed which encompasses effective implementation of PI control using XILINX SPARTAN3E. The experimental results of soft switching boost converter illustrate different aspects of soft switching techniques in this work. Simulations are employed to further corroborate the results.

The front-end power factor correction (PFC) converter is a key component used in modern telecommunications equipment. The boost topology is the most popular one in PFC applications. Based on the flow of current through the energy storing inductor, the boost converter can operate in continuous conduction mode (CCM), discontinuous conduction mode (DCM), or critical conduction mode (CRM). The boost converter operating in DCM and CRM modes is typically easier to control, but it has higher peak-to-peak current ripple, which increases the RMS inductor current [

Interleaving will reduce magnetic volume of the inductor and has the added benefit of reducing RMS current in the boost capacitor. The switches are turned ON and OFF by pulse-width modulation (PWM) technique. But this PWM technique increases the switching losses thereby reducing the efficiency of the converter. To overcome this, soft switching technique is preferred as it provides low input current ripple and reduced losses with ZVS and ZCS [

The closed loop control strategy of DC-DC converters provides better performance, high efficiency, flexibility and protection of the power devices over open loop methods. The voltage control mode is mainly aimed to regulate the output voltage of DC-DC converter which maintains a precise output voltage regardless of variation in load conditions. A PI controller attempts [

The soft switched IBC with FPGA-based digital PI controller has been implemented [

A two-phase soft switched interleaved boost with simple auxiliary commutation circuit is shown in

Ø Low input current ripple due to interleaved technique.

Ø ZVS turn on of the active switches.

Ø ZCS turn off of the active switches.

Ø Components voltage ratings are highly reduced.

Ø Reduced voltage stresses of switches and diodes.

Ø Extendibility to desired voltage gain and power level.

The design equations for the proposed IBC are as follows:

The inductance value can be calculated as

where,

D = Duty cycle,

Output capacitance is

where,

D =Duty cycle,

The output voltage is

where,

D = Duty cycle.

Digital PI control algorithm is implemented because of its good robustness and reliability. By using PWM control, regulation of output voltage is achieved by suitably selecting the duty cycle of the switches.

The Proportional Plus Integral P-I action provides the dual advantages of fast response due to P-action and the zero steady state error due to I-action (

The analytical equation is:

where,

K_{P} = proportional gain,

K_{i} = integral gain,

e = error in % of full scale range,

P_{i}(0) = value of integral term at t = 0.

Taking Laplace transform of Equation (1) will result in,

Also, the transfer function of PI controller is

where,

H(S) is transfer function of PI controller.

Using bilinear transform, transforming Equation (3) into digital domain gives the transfer function of digital PI controller.

The implementation of digital PI controller is based on the converter specifications. The K_{p} and K_{i} obtained are K_{p} = 1, and K_{i} = 0.25.

The implementation of digital PI controller is designed by the interconnection of the comparator, counter, multiplier, adder and subtractor blocks. The K_{p} and K_{i} values are multiplied with the error signal. The error signal is generated by comparing with set point voltage and feedback from output voltage of the converter. The ramp signals are generated with switching frequency of 30 kHz using up counter from the Xilinx blocks. Then the ramp signal and PI controller output is compared and produce the gating signals for two switches T1 and T3 and at the same time the same gating signals are shifted by 45˚ phase shift to drive the two switches T2 and T4 respectively.

Consider the block diagram of FPGA based controller as shown below.

A block diagram representation of FPGA based digital control of Soft Switched IBC is illustrated in

The output voltage of the converter is sensed and then compared to the known reference voltage. A typical digital control stage was formed by 3 blocks: A/D converter, digital PI controller, and Digital Pulse Width Modulator (DPWM). The output voltage is sampled and A/D converted into digital signal. A discrete PI controller computes and a digital pulse-width modulator (DPWM) converts this digital command into a pulse-width signal at a desired switching frequency to drive the switches. In order to attain fast dynamic response, the sample rate

for the output voltage of A/D must be faster than the switching frequency. Moreover, the resolution of the A/D must be high enough to achieve the regulation range of output voltage specification. The simulation parameters for the IBC are shown in

The model of IBC is simulated in MATLAB and it is shown in

The MATLAB simulation results in

The MATLAB simulation results in

A prototype of IBC has been designed in order to verify the simulation results. The DC-DC converter consists of Power MOSFETs IRF840 as main switching device. The optocoupler 6N137 is used to provide digital logic isolation, NOT gate IC4584 to bring back the original pulses and the Hex Schmitt Trigger MC14584B for shaping the pulses. The high voltage, high speed power MOSFET driver IR2110 is employed for driving gate signals to the converter switches. The power supply section provides 5 V and 12 V using LM7805C and LM7812C respectively. The hardware experimental setup is shown in

The measured input and output voltages are shown in

The proto-type hardware setup is designed and tested with an input voltage of 10 V.

The experiment has been conducted on the designed circuit of soft switched interleaved boost converter with 10 V input voltage and maintained the load current to 0.1 A. The commutation process is started by active turn-on of the main switches. It is noted that the drain source voltage V_{ds1} reaches zero while the main switches T1 and T3 were turned ON and there by zero voltage switching operation was realized. The drain source current I_{D1}reaches zero while the main switches T1 and T3 were turned OFF and there by zero current switching operation was realized. Then followed with delay, the same switching operation was realized when the auxiliary switches T2 and T4 were operated in turned ON and turned OFF conditions.

It is desirable to control a power converter using FPGA digital controller. The voltage sensing circuit is used to measure the power converter output voltage signals and are interfaced through an Analog to Digital (A/D) converter to a digital controller. In accordance to the desired PI control, the duty cycle values of the PWM signals to MOSFETs T1 and T3 and delayed PWM signals to MOSFETs T2 and T4 can be calculated as

Component | Parameter |
---|---|

Vin (input voltage) | 10 V |

Switching frequency | 30 KHz |

Duty cycle | 0.78 |

Vout (output voltage) | 45.5 V |

Output current | 0.02 - 0.2 A |

Output power | 1 - 10 W |

Boost inductors L1 and L2 | 1 mH |

Snubber capacitors C1 and C2 | 0.2 µF |

Output filter C0 | 330 µF |

MOSFET On-State Resistance Ron | 0.1 Ω |

Diode On-State Resistance Rd | 0.01 Ω |

Input Voltage in Volts | Load Resistance in Ohms | Set Point Voltage in Volts | Output Voltage in Volts |
---|---|---|---|

10 | 454.5 | 45.45 | 43.91 |

10 | 500 | 40 | 38.97 |

10 | 515.7 | 36 | 34.94 |

10 | 593 | 35 | 34.05 |

10 | 604 | 30 | 30.18 |

10 | 683 | 27 | 27.16 |

10 | 1225 | 24 | 24.15 |

Input Voltage in Volts | Load Resistance in Ohms | Set Point Voltage in Volts | Output Voltage in Volts |
---|---|---|---|

9 | 1000 | 45.45 | 44.96 |

9.5 | 1000 | 40 | 40.43 |

11.2 | 1000 | 36 | 36.3 |

11 | 1000 | 39 | 39.26 |

12.5 | 1000 | 24 | 24.26 |

13.3 | 1000 | 30 | 30.19 |

12 | 1000 | 27 | 27.22 |

Input Voltage in Volts | Load Resistance in Ohms | Set Point Voltage in Volts | Output Voltage in Volts |
---|---|---|---|

10 | 454.5 | 45.45 | 45.45 |

10 | 500 | 40 | 40 |

10 | 515.7 | 36 | 36.1 |

10 | 593 | 35 | 35.6 |

10 | 604 | 30 | 30.2 |

10 | 683 | 27 | 27.3 |

10 | 1225 | 24 | 24.5 |

Input Voltage in Volts | Load Resistance in Ohms | Set Point Voltage in Volts | Output Voltage in Volts |
---|---|---|---|

9 | 1000 | 45.45 | 44.86 |

9.5 | 1000 | 40 | 40.41 |

11.2 | 1000 | 36 | 36.1 |

11 | 1000 | 39 | 39.3 |

12.5 | 1000 | 24 | 24.8 |

13.3 | 1000 | 30 | 29.4 |

12 | 1000 | 27 | 27.32 |

The ramp signals are generated with desired switching frequency using up counter from the Xilinx blocks is compared with the number of counts N-bit value corresponding to the desired duty cycle value and produce the gating signals for two MOSFET switches T1 and T3 and in the same way the delayed gating signals are also compared to drive the auxiliary MOSFET switches T2 and T4. The output voltage can be maintained exactly to the desired set point voltage value irrespective of supply voltage variations and load variations.

The response of soft switched IBC against supply voltage variations and load variations are analyzed and the results are shown in

The experimental readings in

The experimental readings in

In this paper, a simulation and hardware implementation of soft switched IBC was presented. By using this IBC, the output voltage can be maintained constant and it is also found that interleaved boost has the ability in input current sharing as well as reducing the ripple current. Furthermore, this converter always operates in CCM inherently. By using Digital PWM techniques, the proposed converter can achieve faster steady state response when the supply voltage or load changes. Further, research efforts play a major role in constructing high frequency and high efficiency soft switching converter for power factor correction (PFC) of electronic power supplies incorporated in telecommunication switching systems. Any one method of different current control techniques like average current control, hysteresis control and non-linear carrier current control can be utilized by means of digital implementation using FPGA-based digital controller.

Chitravalavan,Dr. R. Seyezhai, (2016) Design and Experimentation of FPGA-Based Soft-Switched Interleaved Boost Converter for Telecommunication System. Circuits and Systems,07,2702-2711. doi: 10.4236/cs.2016.79233