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Vedic mathematics is the system of mathematics followed in ancient Indian and it is applied in various mathematical branches. The word “Vedic” represents the storehouse of all knowledge. Because using Vedic Mathematics, the arithmetical problems are solved easily. The mathematical algorithms are formed from 16 sutras and 13 up-sutras. But there are some limitations in each sutra. Here, two sutras Nikhilam sutra and Karatsuba algorithm are considered. In this research paper, a novel algorithm for binary multiplication based on Vedic mathematics is designed using bit reduction technique. Though Nikhilam sutra is used for multiplication, it is not used in all applications. Because it is special in multiplication. The remainder is derived from this sutra by reducing the remainder bit size to N-2 bit. Here, the number of bits of the remainder is constantly maintained as N-2 bits. By using Karatsuba algorithm, the overall structure of the multiplier is designed. Unlike the conventional Karatsuba algorithm, the proposed algorithm requires only one multiplier with N-2 bits only. The speed of the proposed algorithm is improved with balancing the area and the power. Even though there is a deviation in lower order bits, this method shows larger difference in higher bit lengths.

Vedic Mathematics is the technique used in an Ancient India for solving arithmetical problems mentally and in easier way. It contains 16 formulas and 13 sub-formulas. These sutras are used in solving complex computations, and executing them manually. It is operated on 16 sutras and 13 up-sutras. The algorithms and principles of all sutras were given in [

In [

The iterative algorithm for Nikhilam sutra was presented in [

In [

In [

From the survey, Tridhava multiplier can be used for any range of inputs. Different papers were proposed based on the modification in the adders. Though Nikhilam sutra covers all range of inputs, it is efficient when the multiplicands are closer to the multiple of 10. When it is implemented for binary numbers, normally 2’s complement will be taken. The changes are made in the portion of adders. Similarly, Karatsuba algorithm is good for higher order bits. In Karatsuba algorithm, three multipliers are required along with shift operations. But in the proposed method, Karatsuba and Nikhilam sutras are combined. The multiplier required is reduced to one and the number of bit to the multiplier is reduced by two.

First, Nikhilam Navatascharam Dashtah sutra means all from 9 and last from 10. The Sutra is well explained for multiplication of decimal numbers. The steps for multiplying decimal numbers using this sutra are given below.

1. The nearest base value of multiplicands is considered. Let us assume the multiplicands are A and B.

2. The remainders of A and B are calculated by subtracting the chosen base value from step 1.

3. The product of remainders of A and B are computed and considered as Right part of final product.

4. The Left part can be computed in three ways. The methods are listed below.

a) The two multiplicands A and B are added and the nearest base value is subtracted from the sum A and B. LP = A + B-10.

b) The Left part is calculated by adding the remainders of A and B with Base value.

c) The remainders of A and B are crossly added with the multiplicands A and B.

5. The Final result is attained by removing the demarcation between LP and RP and concatenating the same.

The remainder is derived using this sutra. Based on the type of the remainder, the algorithm is developed. The two types are:

a) Positive remainder.

b) Negative remainder.

The mathematical expression explaining this sutra is given in Equation 1. Let A and B are the two input numbers. The product P is derived as follows:

Here x acts as base B and it is considered as multiple of 10 depending upon the closeness of multiplicands. The remainders of A and B are known as “a” and “b” respectively. The product “ab” denotes the Right Part (RP). The Left Part (LP) is represented by the first term in (1).

The Karatsuba algorithm is suited well for multiplying very large numbers. It is a divide and conquer method, in which the number is divided in to Most Significant half and Least Significant half. The multiplication operations are replaced by addition operations and hence the delay of the algorithm is reduced. This algorithm is more efficient when the number of inputs increase. The algorithm is optimal if width of inputs is more than 16 bits.

The numbers are divided as follows

where A_{l}, B_{l} and A_{r}, B_{r}_{ }in Equation 2 are the most significant half and least significant of the numbers A and B respectively and “n” represents the number of bits. Then, the product can be written as,

From Equation (3), four multiplications and two shift operations are needed. The number is divided equally into two parts. This method is efficient for higher bit length.

In the proposed method, both Nikhilam sutra and Karatsuba algorithm are combined. Using Nikhilam sutra, the remainder is calculated from the nearest value of base 2 by taking 2’s complement. Afterwards, the multiplication is done using Karatsuba algorithm. By doing this, the multiplication required is less.

Let A and B are the numbers and they can be written using Karatsuba algorithm as,

The remainders are derived using Nikhilam Sutra in such a manner that the number of bits for remainder is always N-2. Four modules are generated for different combination of removed MSB values. The weight of remainder is reduced. Then the product is derived as follows,

while comparing (3) and (5), the proposed algorithm requires only one multiplier. And there is no change the shift operation. The multiplier used in the proposed algorithm requires only N-2 bits. Therefore, proposed work reduces the number of multipliers as well as the number of bits of multiplier. The sign will be selected based on the remainder type of A and B. The example for proposed algorithm is shown below:

Input: A, B

Output: P

Step 1: A and B are the multiplicands with N bits. Their remainders are calculated by removing first two bits and taking 2’s complement for the remaining N-2 bits. (N-1, N-2 = 11)

r1 = complement (A)

r2 = complement (B)

Step 2: Multiplying both remainders using N-2 × N-2 bit multiplier

Step 3: Shifting A by N times (P_{2})

Step 4: Shifting the remainder r_{2} by N times (P_{3})

Step 5: The product can be calculated as,

The proposed architecture for the multiplier for the MSB values 11 is given in

Input: A, B

Output: P

Step 1: Calculating remainders for both multiplicands by removing first two bits. If the removed bits are 10, the remainders are determined by taking the numbers without the MSB values. (i.e. N-1, N-2 = 10)

_{1} = A (without first two bits)

_{2} = B (without first two bits)

Step 2: Multiplying both remainders using N-2 × N-2 bit multiplier (P_{1}).

Step 3: Shifting A by N-1 times (P_{2})

Step 4: Shifting the remainder by N-1 times (P_{3})

Step 5: The product can be calculated as,

The architecture for the proposed algorithm is shown in

Input: A, B N bits

Output: P 2N bits

Step 1: Calculating remainders for both multiplicands by removing first two bits. If the removed bits are 01, the remainders are determined by taking the numbers without the MSB values. (i.e. N-1, N-2 = 10)

_{1} = complement (A)

_{2} = complement (B)

Step 2: Multiplying both remainders using N-2 × N-2 bit multiplier (P_{1}).

Step 3: Shifting A by N-1 times left side (P_{2})

Step 4: Shifting r2 by N-1 times left side (P_{3})

Step 5: The product can be calculated as,

The architecture for the proposed algorithm is shown in

Input: A, B

Output: P

Step 1: Calculating remainders for both multiplicands by removing first two bits. If the removed bits are 00, the remainders are determined by taking the numbers without the MSB values. (i.e. N-1, N-2 = 10)

_{1} = complement (A)

_{2} = complement (B)

Step 2: Multiplying both remainders using N-2×N-2 bit multiplier (P_{1}).

Step 3: Shifting A by N-2 times (P_{2})

Step 4: Shifting r_{2} by N-2 times (P_{3})

Step 5: The product can be calculated as,

The architecture for this algorithm is shown in

derived is positive and for the other combinations the remainders are negative. For negative remainders, the complement should be taken. The input A is shifted N-2, N-1 or N times according to the MSB bits of B. For remainder multiplication, multiplier with N-2 bit is used. The remainder of B is shifted N-1, N-1 or N times. Finally, all the terms added or subtracted according to the algorithm. A simple control circuit is used to select the operation in adder/subtractor module. This architecture is suitable for any input range of inputs. The multiplication is required only when both inputs are nonzero values. The multiplexer is used to reduce the power dissipation when the remainder is zero. In [

AVedic Mathematics is a technique to solve the arithmetic operations easily and mentally. Traditionally, Urdhva Tiryakbhyam Sutra is known as Vedic Multiplier because it covers all range of inputs. It means “vertically and crosswise”. In most of the research papers [

Depending upon the value on Right part, correction is made on left part. In the proposed method, all range of inputs can be given. Karatsuba algorithm is efficient for higher order multipliers. Karartsuba multiplier uses three multipliers based on Equation. (3). But in the proposed method, the numbers of multiplier is reduced to one and number of bits of the multiplier is reduced to N-2. Here, Nikhilam sutra and Karatsuba algorithm are combined to get the high speed. The implementation for various Vedic multipliers is done using Xilinx Spartan 3e kit. In the main module, the proposed multiplier is itself used. The comparison with Vedic multiplier for delay is listed in

The proposed algorithms are written in VHDL and simulated using ModelSim . The simulation result for 32 bit size is shown in

Device | Methods | Delay in nS | |||||
---|---|---|---|---|---|---|---|

4 Bit | 8 Bit | 16 Bit | 32 Bit | 64 Bit | |||

Xilinx Spartan 3e | Urdhva Tiryakbhyam Sutra [ | 11.412 | 30.628 | 49.413 | 85.359 | 155.364 | |

Karatsuba Algorithm [ | 15.231 | 31.029 | 46.811 | 82.834 | 150.922 | ||

Vedic-Karatsuba Algorithm [ | 10.197 | 18.005 | 27.81 | 49.864 | 92.448 | ||

Karatsuba-Urdhva Multiplier | 15.072 | 18.492 | 26.398 | 42.174 | 87.235 | ||

Proposed Karatsuba-Nikhilam Multiplier | 14.561 | 16.916 | 22.147 | 32.156 | 64.198 | ||

Xilinx Spartan 6 | Urdhva Tiryakbhyam Sutra [ | 9.247 | 26.321 | 49.413 | 77.924 | 142.638 | |

Karatsuba Algorithm [ | 10.124 | 28.965 | 46.811 | 74.529 | 138.953 | ||

Vedic-Karatsuba Algorithm [ | 8.621 | 18.005 | 27.81 | 41.953 | 88.627 | ||

Karatsuba-Urdhva Multiplier | 11.632 | 25.362 | 26.398 | 37.439 | 69.837 | ||

Proposed Karatsuba-Nikhilam Multiplier | 10.564 | 23.624 | 22.147 | 28.634 | 49.391 | ||

Methods | Delay in nS | |||||
---|---|---|---|---|---|---|

4 Bit | 8 Bit | 16 Bit | 32 Bit | 64 Bit | ||

Array Multiplier | 15.269 | 31.111 | 62.437 | 123.387 | 240.542 | |

Shift and Add Multiplier | 15.677 | 33.840 | 63.089 | 124.112 | 243.619 | |

Braun Multiplier | 13.088 | 23.331 | 62.437 | 127.776 | 242.325 | |

Wallace Tree Multiplier | 12.756 | 22.863 | 44.258 | 87.776 | 152.584 | |

Proposed Karatsuba-Nikhilam Multiplier | 14.561 | 16.916 | 22.147 | 32.156 | 64.198 | |

In this research paper, successive approximation of Vedic multiplier is proposed for high speed applications. The algorithm of Karatsuba is modified to reduce the number of multipliers required in the calculation. Instead of splitting the binary number into half, the number is split based on remainder value. The remainder is calculated using Nikhilam Sutra such that the number of bits is reduced to N-2. By combining Nikhilam Sutra and Karatsuba algorithm, the number of bits to the multiplier is reduced. Four modules were created based on remainders. From the results’, it is clear that the proposed method produces output faster than other methods. This hybrid multiplier is best suited for multiplying large numbers in high speed applications.

S. K. Manikandan,C. Palanisamy, (2016) Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics with Bit Reduction Technique. Circuits and Systems,07,2593-2602. doi: 10.4236/cs.2016.79224