^{1}

^{*}

^{1}

^{2}

Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computing, etc. In industrial automation, comparators play an important role in segregating faulty patterns from good ones. In previous works, these comparators have been implemented with more number of reversible gates and computational complexity. All these comparators use propagation technique to compare the data. This will reduce the efficiency of the comparators. To overcome the problem, this paper proposes an efficient comparator using (Thapliyal Ranganathan) TR gate utilizing full subtraction and half subtraction algorithm which will improve the computation efficiency. The comparator design using half subtraction algorithm shows an improvement in terms of quantum cost. The comparator design using full subtraction algorithm shows effectiveness in reducing number of reversible gates required and garbage output.

Moore’s law states that number of transistors in a chip doubles every two years but chip size decreases. This cannot be reduced greatly which will lead to more power consumption. This paves the path to new technologies “Reversible logic” and “Quantum dot Cellular Automata (QCA)”. As stated by Launder during logical computation, a bit of information is lost. It dissipates 2ln (KT) energy, where K is Boltzman constant and T is temperature. Present day computers are formed of digital logic circuits where one bit of information is lost for every computation. This is called irreversible logic [

Equal number of inputs and outputs

Unique nature of outputs one to one mapping.

The Input and Output mapping is shown in

Minimum garbage output

No feedback

No fan out

Minimum number of reversible gates to be used

Minimum number of constant inputs.

The number of 1 × 1 or 2 × 2 reversible gates needed to design a reversible logic circuit is called quantum cost.

The number of reversible gates including 3 × 3 and 4 × 4 reversible gates needed to design system is the number of reversible gates required.

The unused output in a reversible circuit is called garbage output.

Total logic calculation is the number of XOR, AND, NOT logic function used in the reversible circuit. α indicates number of XOR logic in the circuit; β indicates number of AND logic in the circuit and γ indicates number of NOT logic in the circuit.

Reversible gates are classified as 2 × 2 gates, 3 × 3 gates and 4 × 4 gates. Example for 2 × 2 gates is Feynman gate, and for 3 × 3 gates are Taffoli gate and Peres gate. The Classification of Reversible Logic Gates is given in

The basic reversible gates are shown in

Thapliyal proposed a three input reversible gate called TR gate [

The Reversible TR gate is given in

Research in reversible logic is getting importance today. Thapliyal and Srinivasan proposed a new reversible (Thapliyal Srinivasan Gate) TSG gate [

for mathematical computation. These basic mathematical calculations form the base for modern VLSI architecture. Thapliyal discussed about performance of Vedic multipliers on (Field Programmable Gate Array) FPGA [

Research in reversible logic is getting importance today. Nagamani et al. presented reversible 1 bit comparators [

This paper designs a reversible comparator using TR gate proposed by Thapliyalusing full subtraction and half subtraction algorithm and analyzes the performance of the comparators in terms of quantum cost, number of gates and garbage output. The rest of the paper discusses proposed comparator design in Chapter 2, results and discussion in Chapter 3 and finally conclusion.

In present day industrial automation, comparators play a major role. Digital comparator are used in computer processors, and moreover it can be used in some industrial automation devices that contrast visual images with digital images, as in the case of mechanical engineering industry that relies on computer-aided drafting (CAD) programs to check good products from faulty ones. They also can be employed to convert analog signals into digital patterns. A digital comparator also can be used along with a number of other devices to act as a monitor in an industrial setting to monitor accurate state of a machine. In view of importance of comparator in many industrial applications, this paper proposes reversible comparator design using TR gate proposed by Thapliyal (it is used as full subtractor). The comparator is designed with full subtraction algorithm and half subtraction algorithm. The proposed design is compared with previous works in terms of Quantum Cost, number of reversible gates, number of garbage outputs.

The comparator system consists of data segregator, comparator using the above algorithms and equvalence checker. The comparator system is shown in

Reversible comparator is designed based on the subtraction algorithm. The paper uses full subtraction algorithm to compare 4 bit data. Carry is propagated between the bits. The same algorithm is used to design reversibe comparator based on TR gate subtractor. The design using TR gate requires 8 TR gates. To implement a subtractor module, 2 TR gates are needed. For 4 bit subtraction 8 TR gates are required. When end carry arises, A < B. When end carry is “0”, A > B. When all the difference bits and end carry bits are zero, then A = B. Each pair of TR gate acts as full subtractor. The architecture diagram for reversible comparator using full subtraction algorithm is shown in

In the comparator architecture shown below Q0-Q3 represents difference bits, R0-R3 represents borrow bits. For bits if borrow occurs Cout is “1”. A < B. If borrow does not occur and if the difference is zero, then A = B. If borrow does not occurs but if the difference is not zero then A > B. It involves carry propagation, so it is expected that computation delay will be little bit higher.

Reversible comparator is designed based on the half subtraction algorithm. This paper uses half subtraction algorithm to compare 4 bits of data. Carry is not propagated between the bits. Instead the carry generated in each bit is used to judge the comparison. The 4 bit data is divided into two sets of data LSB and MSB. The algorithm is explained below. The algorithm is used to design reversibe comparator based on TR gate subtractor. The design using TR gate requires 4 TR gates. To implement a half subtractor module, 1 TR gates is needed. For 4 bit subtraction 4 TR gates are required. The architecture diagram for reversible comparator using half subtr- action algorithm is shown in

In the comparator architecture shown below D0-D3 represents difference bits, B0-B3 represents borrow bits. The data is verified from MSB to LSB. For MSB bits if borrow occurs. A < B. If borrow does not occur and if the difference is zero, then A = B. If borrow does not occurs but if the difference is not zero then A > B. To check the last two conditions equivalence checker is used. Since data verififcation starts from MSB to LSB, it is expected that computation delay will be less.

ALGORITHM

Ø Segregate the 4 bit data and perform half subtraction on each of the minuend and subtrahend seperately.

Ø Check from MSB, if carry occurs in the MSB, then subtrahend is greater.

Ø If carry does not occur in MSB and difference is also “1”, then minuend is greater.

Ø Else if carry does not occur in MSB and difference is also “0”, then check in next bit position if carry occurs then subtrahend is greater and repeat this for next set of bits.

Ø If carry does not occur and difference is also ‘0’, then the two bits are equal.

Ø If carry does not occur and difference results then minuend is greater.

The equivalence checker consists of feynman gates. The gate uses EXOR logic which is used to compare the data obtained from comparator with predefined pattern. The equivalence checker is given in

The proposed method is verified for functional verification in Xilinx 9.2 using verilog simulator. The results for Comparator using the full subtraction algorithm is shown in

In

In

a1 and b1 corresponds to MSB bits. c1 and d1 corresponds to LSB bits are inputs, q2 and q3 corresponds to difference bits and r and r1 corresponds to carry bits. Here a1 and c1 are minuend, b1 and d1 are subtrachend. If a1 = 2, b1 = 2, c1 = 1 and d1 = 0, then the difference occurs in q3 and carry does not occur.This indicates miuend is greater.

Case 2 consider the data “32” & “22”. The data are segregated into MSB and LSB bits as discussed below.When the data are subtracted from MSB bits, MSB bits are not equal difference occurs and carry does not occur. The difference is “1” and borrow is “0” which indicates miuend is greater. If a1 = 3, b1 =2, c1 =2 and d1 = 2, then the difference occurs in q2 and carry does not occur. This indicates miuend is greater.

Case 3 consider the data “21’ & “22”. The data are segregated into MSB and LSB bits as discussed below.When the data are subtracted from MSB bits, MSB bits are equal difference does not occurs and carry does not occur.So next LSB bits are considered, “1” and “2” when subtracted difference is”1’ and carry is “1”. If a1 = 2, b1 = 2, c1 = 1 and d1 = 2, then the difference occurs in q3 and carry also occurs. This indicates subtrahend is greater.

Case iv consider the data “22” & “32”. The data are segregated into MSB and LSB bits as discussed below.When the data are subtracted from MSB bits, MSB bits are not equal difference occurs and carry also occur. The data “2” and “3” when subtracted difference is “1” and carry is “1”. If a1 = 2, b1 = 3, c1 = 2 and d1 = 2, then the difference occurs in q2 and carry also occurs. This indicates subtrahend is greater.

TheComparitive analysis of reversible comparators is given in

In the existing technique [

In the existing technique [

In the proposed method, TR gate and Feynman gate are used in half subtraction mode which generates less garbage output and less quantum cost. The data is checked from MSB to LSB. If in the MSB, carry generated then there is no need for comparison of successive bits. This reduces delay in comparison for higher value of MSB.

The Comparitive analysis of reversible comparators for 8 bit comparator is shown in

From

In this paper, a reversible comparator using TR gate based on full subtraction algorithm and half subtraction

Number of Gates | Number of Garbage | Quantum Cost | |
---|---|---|---|

Comparator proposed in [ | 10 | 15 | 42 |

Previous Comparator [ | 25 | 23 | Unknown |

Existing Comparator [ | 16 | 17 | 50 |

Comparator using TR gate using Half subtraction method | 12 | 12 | 32 |

Comparator using TR gate using Full subtraction method | 9 | 9 | 49 |

Architecture | Number of Gates | Number of Garbage | Quantum Cost |
---|---|---|---|

Existing Comparator [ | 42 | 135 | |

Existing Comparator (Peres gate and BJN gate) [ | 24 | 16 | 80 |

Existing Comparator (Taffoli gate and BJN gate) [ | 32 | 16 | 128 |

Existing Comparator (Fredkin gate and BJN gate) [ | 40 | 48 | 184 |

Existing Comparator (TR and BJN gate) [ | 24 | 16 | 96 |

Comparator proposed in [ | 20 | 30 | 84 |

Previous Comparator [ | 50 | 46 | Unknown |

Existing Comparator [ | 32 | 34 | 112 |

Proposed Comparator using TR gate using Full subtraction method | 18 | 18 | 98 |

Proposed Comparator using TR gate using Half subtraction method | 24 | 24 | 64 |

algorithm was presented and analyzed with existing comparators. It is found that comparator designed half subtraction algorithm using TR gate shows effectiveness in terms of quantum cost but at the expense of number of reversible gates and garbage output. Reversible comparator using full subtraction algorithm proposed is performing better in terms of number of reversible gates and garbage output since equivalence checker circuit is not needed. The same algorithm may be implemented with Delay elements in between by principle of retiming to reduce critical path delay. The future scope of the work is to realize these reversible logic gates in DNA molecules and implement these arithmetic systems so as to reduce power consumption.

Subramanian Saravanan,Ila Vennila,Sudha Mohanram, (2016) Design and Implementation of an Efficient Reversible Comparator Using TR Gate. Circuits and Systems,07,2578-2592. doi: 10.4236/cs.2016.79223