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As the demand for high voltage, high power inverters are increasing and there is a problem of connecting a power semiconductor switch directly to a high voltage network. As a part of this the multilevel inverters had been introduced. As a part of this, several researches had been done for the development of multilevel inverters. The commercially available and extensively studied topologies for multilevel voltage output are Neutral Point Clamped (NPC), Cascaded Half Bridge (CHB) and Flying Capacitor (FC) converters. However, with these existing topologies, there is a significant increase in the number of power switches and passive components. Thus it leads to more complex control circuitry and overall cost of the system increase with increase in the output levels. In this paper, a novel multilevel inverter is proposed in which it employs additive and subtractive topology to get higher output levels. This approach significantly reduces the number of power switches needed as compared to existing topology. The present developed multilevel inverter can generate only five voltage levels. With this proposed topology the multilevel inverter can be modified to nine-level inverter. Moreover modified hybrid multicarrier Pulse Width Modulation (PWM) technique can be implemented in the proposed multilevel inverter in order to obtain uniform switch utilization and lower THD. An appropriate modulation scheme is presented and also the proposed concept is analyzed through simulation studies.

In the recent technologies, multilevel voltage source inverters have emerged as a viable solution for the conversion of Direct Current (DC) to Alternate Current (AC) applications. As the name defined Multilevel Inverter (MLI) is used to generate different voltage levels, i.e., voltage levels greater than three or more. MLI is defined as a linkage structure of multiple input DC sources and power semiconductor devices to generate a staircase waveform. As compared to the conventional inverters, voltage stress experienced by the power switches is much lower in the case of MLIs. In addition to this, a better harmonic profile wave form can be obtained from MLIs as compared to two-level waveform conventional inverters. MLIs have other advantages also such as reduced dv/dt stress on load and possibility of fault tolerant operation. For low power applications, the researchers are exploring the implementation of MLIs. By increasing the number of levels we can enhance the quality of multilevel waveform. But however, it adversely increases the number of power semiconductor devices and accompanying gate driver circuits. As a result of this the system complexity and cost gets increased and thus reduce the system reliability and efficiency. Therefore in order to achieve high resolution waveform, practical considerations necessitate reduction in the number of switches and gate driver circuits.

The topologies which have been extensively studied and available for multilevel voltage output are Neutral Point Clamped (NPC), Cascaded H-Bridge (CHB) and Flying Capacitor (FC) converters. With the increase in the number of output levels, there is a significant increase in the number of power switches and overall cost of the system. Therefore researchers through various approaches focus to reduce the component count in multilevel topologies. These approaches can be broadly classified into mainly three categories such as topological changes use of asymmetric sources, combination of topological changes and asymmetric source configurations. In Section 3, we are dealing with a topology of switched DC source topology [

In this topology alternate DC sources are linked in opposite polarities via power switches. This topology shows similarity with the CHB topology in two ways such as it needs multiple isolated input DC voltages and input DC voltage levels are combined in to all additive values. The linkage structure in this topology can be obtained by connecting the higher potential terminal of the preceding source to the lower potential terminal of the succeeding source and vice versa via power switches. These power switches can be implemented using a transistor device such as MOSFET and IGBT with an antiparallel diode. The Switched DC Source topology is described with a single phase nine-level inverter as shown in _{1}, T_{2}, T_{3} and their complimentary switches_{1} and E_{2}.

The five voltage levels are obtained by the proper switching of these switches. With this topology we are generating five voltage levels such as +V_{dc}, −V_{dc}, +2V_{dc}, −2V_{dc} and zero for E_{1} = E_{2} = V_{dc}. The output voltage E_{1} is obtained when switches T_{1}, _{3}, _{2}. The output voltage (E_{1} + E_{2}) is obtained by turning ON the switches T_{1}, _{3}. Thus correspondingly we get other output voltages such as −(E_{1} + E_{2}), −E_{1} and E_{2}. With this topology if we are stepping up five level to nine level it needs 4 DC sources and 10 switches. But if we are implementing a new topology known as “Additive and Subtractive” topology, we are able to generate nine level with 2 DC sources and 8 switches. Therefore with this topology we can reduce the component count to a maximum limit. The detailed study of this topology is further discussed in the next section.

Nowadays MLIs are becoming more popular due to reduced voltage stress across power switches and low THD output voltage wave form. However as level increases the device count also increases. So in order to obtain maximum number of levels in output waveform with limited number of components we are proposing a novel topology known as additive and subtractive topology. This paper presents a novel multilevel topology which is capable of obtaining all additive and subtractive combinations of input DC levels in the output waveform. Here the actual number of levels generated depends on the DC source arrangement. The DC sources and switches are arranged in such a manner that it is possible to obtain all possible combinations in the output, i.e., if “n” number of DC sources are present, then “4n” power switches are required to obtain all possible combinations. From this concept for the proposed topology total number of power switches required is “4n”.

The working principle of proposed topology is described with the help of a single phase nine-level inverter. Here it consists of two input asymmetric DC sources E1 and E2, such that E2 < E1 as shown in

1) “Unary” arrangement will result if all the DC sources are equal, i.e.

2) “Binary” arrangement will result if the DC sources make a geometric progression with a factor of “1/2”, i.e.

4) “Trinary” arrangement will result if the DC sources make a geometric progression with a factor of “1/3”, i.e.

The proposed topology is described with a nine-level inverter with two input DC sources as shown in

The proposed inverter can be realized with self-commutating power switches like MOSFET’s and IGBT’s. It is also important to note that the switches at positions T_{2} and _{2} and_{1} + E_{2}) is required and switches_{3} and T_{1} are ON, then the anti-parallel diode of switch _{2}. Thus it acts as ON switch, thereby short-circuiting the source E_{2}. A similar phenomenon happens when switches T_{4}, _{1} + E_{2}). Under such conditions, the anti-parallel diode of T_{2} gets a forward-biasing potential difference equal to E_{2}, thereby short-circuiting the source E_{2}. Therefore, at both positions T_{2} and

For the multilevel inverter modulation control we can use either Multicarrier PWM or space vector modulation techniques [

In the proposed modulation scheme, for all the carrier waveforms above the time-axis, the results of comparison

with the reference sine wave are “1” or “0”. For all the carrier waves below the time-axis, the results of comparison with the reference sine wave are “0” or “−1”. Here we are implementing a new modulation technique known as multi carrier pulse width modulation technique [

The switching signals for the switches are obtained from this aggregate signal. The switching signals thus obtained are known as D-states. Thus D-states are generated by combining it with switching pattern and saturation limits. Here it consists of a total of nine lookup tables as shown in

Using MATLAB/Simulink the proposed structure is simulated to get nine-level output. The DC sources are taken

such that E_{1} = 12.5 V and E_{2} = 37.5 V. In the previous section modulation scheme is described and it is considered for inductive load. The inverter is operated in open loop mode. With this proposed topology it produces nine voltage levels and it is shown in

As MLIs are gaining interest, efforts are being directed towards reducing the device count for increased number of output levels. As a part of this, a new topology known as additive and subtractive topology had developed to reduce the device count. Instead of using cascaded inverter topology and switched DC source topology, the proposed topology is better because it has less control complexities, less cost and gives less percentage of THD. This topology can be effectively employed only for applications where isolated DC sources are available. On behalf of this, several surveys about MLIs had been conducted. Based upon these surveys a novel multilevel inverter can be developed which employs additive and subtractive topology. By implementing this topology, it

nullifies the drawbacks of switched DC source topology and thus improves the reliability. In addition to this hybrid PWM modulation technique can be applied for the uniform switch utilization and even power distribution.

V. Prasannamoorthy,P. Sundaramoorthi,Merin Jacob, (2016) A Novel Multilevel Inverter Employing Additive and Subtractive Topology. Circuits and Systems,07,2425-2436. doi: 10.4236/cs.2016.79209