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Multilevel inverter has played a vital role in medium and high power applications in the recent years. In this paper, Reduced Switch Count Multi Level Inverter structure (RSCMLI) topology is presented with different pulse width modulation techniques. The harmonic level analysis is carried out for the reduced switch count multilevel inverter with the different PWM technique such as with Alternate Phase Opposition Disposition (APOD) method, In Phase Disposition (IPD) method and multi reference pulse width modulation method for five level, seven level , nine level and eleven level inverter. The simulation results are compared with the cascaded H Bridge Multi Level Inverter (CHBMLI). The nine level RSCMLI inverter with APOD method is used for the Distribution Static Synchronous Compensator (DSTATCOM) application in the nonlinear load connected system for power factor improvement. The result shows that the harmonic level and the number of switches required for RSCMLI is reduced compared to CHBMLI. RSCMLI employed in DSTATCOM improves the power factor and harmonic level of the system when it is connected to the nonlinear load.

Multilevel inverter is used in many applications in industries and in other fields which suits for high power and high voltage applications. The two level inverter is used in the low voltage and low power applications. For medium and high voltage application with two level inverter, the voltage stress on each power electronic switch and its switching losses will be more and harmonic level will be increased, it also requires large filter size. Multilevel inverter overcomes this problem and the voltage level can be increased to a required level which suits for medium to high voltage and high power application. Multilevel inverter topologies are classified into three types Diode Clamped Multilevel Inverter, Flying Capacitor Multilevel Inverter, Cascaded H Bridge Multilevel Inverter. Among these Cascaded H Bridge MLI is simple in structure and requires fewer components. As the level goes on increasing the semiconductor device required, it will be more and the structure becomes large. Multilevel inverter with less switch count is the interest of the researchers in the recent years where it can generate required level of output voltage with minimum switch count. There are different topologies for reduced switch count MLI which has been listed in [

Multilevel inverter topologies are used in the application of custom power electronic device to mitigate power quality issues. Distribution Static Synchronous Compensator (DSTATCOM) is a device used to mitigate the power quality issues like voltage sag, swell, power factor improvement and reactive power compensation. MLI is used in the voltage source inverter part of the DSTATCOM [

From [

DSTATCOM is connected in shunt to the three phase supply of 415 V, 50 Hz system at the point of common coupling point (PCC) connected to a nonlinear load of rectifier unit with RC load. The DSTATCOM structure consists of a dc energy source connected to the voltage source inverter (VSI) part with the reduced switch count topology structure and is connected to the ac system with filter unit through coupling transformer. The RSCMLI structure of nine level is used in the VSI part of DSTATCOM.

The reduced switch count multilevel inverter structure consists of a conventional H bridge unit with bidirectional switches in it to get the required voltage level with a single dc source and with voltage dividing capacitors.

N-level requires [((N − 1)/2) + 3] switches.

The pulse width modulation technique is the key part in the multilevel inverter to trigger the switches at the proper instant and to get the required level of output voltage. In this paper the following PWM methods are used for the reduced switch count MLI in order to get the required level of output voltage and the harmonic analysis is carried for the RSCMLI with these PWM techniques. For this RSCMLI topology with the PWM techniques switches S2, S4 operates at fundamental frequency and other switches are operating at switching frequency.

In the Multicarrier Alternate Phase Opposition Disposition method [

where m is the modulation index, V_{m} is the magnitude of the reference signal, n is the number of carrier signals required for an N level and V_{c} is the magnitude of the single carrier signal. For 5 level inverter it requires two carrier signal, for 7 level inverter it requires three carrier signal, for 9 level inverter it requires four carrier signal, for eleven level inverter it requires five carrier signal. For the eleven level inverter the modulation index is calculated as m = 4.5/(5 × 1)=0.9 , where V_{m} = 4.5, V_{c} = 1, n = 5.

The reference signal is compared with the carrier signals to generate gate pulse for the switches and the output of the required level will be obtained. For the eleven level inverter, V_{carrier5}(V_{c}_{5}) is compared with V_{ref} until V_{ref} exceeds the magnitude of V_{c}_{5} then V_{ref} is compared with V_{c}_{4} until V_{ref} exceeds the magnitude of V_{c}_{4} then V_{ref} is compared with V_{c}_{3} until V_{ref} exceeds the peak magnitude of V_{c}_{3} then V_{ref} is compared with V_{c}_{2} until V_{ref} exceeds the magnitude of V_{c}_{2} then V_{ref} is compared with V_{c}_{1} until it exceeds the magnitude of V_{c}_{1} and then goes on. Switches S_{2} and S_{4} operates at the fundamental frequency and the remaining switches S_{1}, S_{3}, S_{5}, S_{6}, S_{7} and S_{8} operates at the switching frequency.

The multicarrier IPD method is similar to the multicarrier APOD method whereas in this method the carrier signals are in same phase and are arranged same as the above method and the functional method is same as explained in the above method is shown in

In this method multi reference PWM technique is followed where it requires multiple reference signal and with

single carrier signal to generate gate pulse. This method [_{ref}_{1}, V_{ref}_{2}, V_{ref}_{3}, V_{ref}_{4}, and V_{ref}_{5}) signals and with a carrier signal (V_{carrier}). V_{ref1} is compared with V_{carrier} if V_{ref}_{1} exceeds the magnitude of carrier signal V_{carrier} then V_{ref}_{2} is compared with the carrier signal till it exceeds the peak magnitude of V_{carrier} then V_{ref3 }is compared with the carrier signal until it exceed the peak magnitude of the carrier signal then V_{ref4} is compared with the carrier signal till it has exceed the magnitude of the carrier signal V_{carrier} then V_{ref}_{5} is compared with the carrier signal until it reaches zero then V_{ref}_{4} is compared with the carrier signal till it reaches zero then V_{ref}_{3} is compared with V_{carrier} until it has reached zero then V_{ref2} is compared with V_{c}_{arrier} till it reaches zero then onwards V_{ref1} is compared with V_{carrier} signal. This method is shown in

The switching sequences for five, seven, nine and eleven level of RSCMLI are given in Tables 1-4.

These techniques are implemented for five level, seven level, nine level and eleven level RSCMLI inverter and the harmonic analysis are carried out for these methods.

The harmonic analysis of the reduced switch count MLI inverter is carried out with the PWM techniques of multicarrier APOD, IPD method and with multireference PWM technique for five level, seven level, nine level

Output Voltage | S1 | S2 | S3 | S4 | S5 |
---|---|---|---|---|---|

+Vdc/2 | 0 | 0 | 0 | 1 | 1 |

+2Vdc/2 | 1 | 0 | 0 | 1 | 0 |

0 | 1 | 1 | 0 | 0 | 0 |

−Vdc/2 | 0 | 1 | 0 | 0 | 1 |

−2Vdc/2 | 0 | 1 | 1 | 0 | 0 |

Output Voltage | S1 | S2 | S3 | S4 | S5 | S6 |
---|---|---|---|---|---|---|

+Vdc/3 | 0 | 0 | 0 | 1 | 0 | 1 |

+2Vdc/3 | 0 | 0 | 0 | 1 | 1 | 0 |

+3Vdc/3 | 1 | 0 | 0 | 1 | 0 | 0 |

0 | 1 | 1 | 0 | 0 | 0 | 0 |

−Vdc/3 | 0 | 1 | 0 | 0 | 1 | 0 |

−2Vdc/3 | 0 | 1 | 0 | 0 | 0 | 1 |

−3Vdc/3 | 0 | 1 | 1 | 0 | 0 | 0 |

Output Voltage | S1 | S2 | S3 | S4 | S5 | S6 | S7 |
---|---|---|---|---|---|---|---|

+Vdc/4 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |

+2Vdc/4 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |

+3Vdc/4 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |

+4Vdc/4 | 1 | 0 | 0 | 1 | 0 | 0 | 0 |

0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 |

−Vdc/4 | 0 | 1 | 0 | 0 | 1 | 0 | 0 |

−2Vdc/4 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |

−3Vdc/4 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |

−4Vdc/4 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |

Output Voltage | S1 | S2 | S3 | S4 | S5 | S6 | S7 | S8 |
---|---|---|---|---|---|---|---|---|

+Vdc/5 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |

+2Vdc/5 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 |

+3Vdc/5 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 |

+4Vdc/5 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 |

+5Vdc/5 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |

0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |

−Vdc/5 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 |

−2Vdc/5 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |

−3Vdc/5 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |

−4Vdc/5 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |

−5Vdc/5 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 |

and eleven level for the modulation index of 1, 0.9 and 0.8. The voltage waveform of these levels with the PWM techniques and the FFT analysis are shown in Figures 7-10 and the results are also compared with the Cascaded H-bridge Multilevel inverter. The results are tabulated in

The result shows that the harmonic level is less in RSCMLI method compared to Cascaded H Bridge MLI. The RSCMLI with APOD PWM method for nine level is applied for DSTATCOM.

The nine level reduced switch count multilevel inverter is used for the application of DSTATCOM in the voltage source inverter (VSI) part for power factor improvement in a nonlinear load connected system and the simulation model of the test system is shown in

The analysis of the system without and with DSTATCOM for power factor improvement is carried out and the simulation results are shown in Figures 12-16 and are tabulated in

The harmonic level of the voltage and current of the system with nonlinear load when the system is connected without DSTATCOM and with DSTATCOM is tabulated in

In this paper, the Reduced Switch Count Multilevel Inverter (RSCMLI) structure topology is analyzed with the Alternate Phase Opposition Disposition method (APOD), In Phase Disposition method (IPD), and with multi reference PWM method. The harmonic analysis for five level, seven level, nine level and eleven level of RSCMLI inverter is carried out with these PWM techniques for the modulation index of 1, 0.9 and 0.8.The re-

Levels | Modulation Index | APOD PWM Method | IPD PWM Method | THD of RSCMLI with Multireference PWM Method (in %) | ||
---|---|---|---|---|---|---|

THD of RSCMLI (in %) | THD of CHBML (in %) | THD of RSCMLI (in %) | THD of CHBMLI (in %) | |||

Five Level | 1 | 14.86 | 16.02 | 14.41 | 19.20 | 14.43 |

0.9 | 19.67 | 23.05 | 19.17 | 26.28 | 19.21 | |

0.8 | 23.34 | 26.01 | 22.05 | 31.26 | 22.11 | |

Seven Level | 1 | 10.27 | 11.05 | 10.66 | 12.87 | 10.66 |

0.9 | 13.36 | 14.01 | 13.08 | 17.88 | 13.08 | |

0.8 | 13.42 | 18.77 | 14.18 | 18.25 | 14.18 | |

Nine Level | 1 | 8.37 | 9.31 | 10.61 | 9.81 | 10.61 |

0.9 | 9.75 | 10.66 | 12.15 | 11.54 | 12.15 | |

0.8 | 9.54 | 9.71 | 10.14 | 10.50 | 10.15 | |

Eleven Level | 1 | 7.38 | 7.50 | 7.84 | 8.09 | 7.85 |

0.9 | 8.05 | 8.10 | 8.08 | 10.44 | 8.09 | |

0.8 | 8.32 | 8.41 | 10.60 | 10.95 | 10.61 |

Parameters | Without DSTATCOM | With DSTATCOM |
---|---|---|

THD of Voltage at source point | 2.83% | 1.25% |

THD of current at source point | 124.04% | 4.53% |

THD of Voltage at PCC point | 8.20% | 3.94% |

THD of current at PCC point | 124.40% | 4.53% |

THD of Voltage at load point | 8.20% | 3.94% |

THD of current at load point | 136.39% | 91.61% |

Power Factor | 0.8339 | 0.9985 |

sults are tabulated in

Sambasivam Rajalakshmi,Parthasarathy Rangarajan, (2016) Analysis of Reduced Switch Topology Multilevel Inverter with Different Pulse Width Modulation Technique and Its Application with DSTATCOM. Circuits and Systems,07,2410-2424. doi: 10.4236/cs.2016.79208

Three phase source: 415 V, 50 Hz; Source impedance = 0.001 Ω, L = 2e − 3H; Nonlinear load: Rectifier unit with RC load R = 100 Ω, C = 370e − 6F.Vdc = 400 V

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