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This paper is designed to introduce new hybrid Vedic algorithm to increase the speed of the multiplier. This work combines the principles of Nikhilam sutra and Karatsuba algorithm. Vedic Mathematics is the mathematical system to solve the complex computations in an easier manner. There are specific sutras to perform multiplication. Nikhilam sutra is one of the sutra. But this has some limitations. To overcome the limitations, this sutra is combined with Karatsuba algorithm. High speed devices are required for high speed applications with compact size. Normally multipliers require more power for its computation. In this paper, new multiplication algorithm for the multiplication of binary numbers is proposed based on Vedic Mathematics. The novel portion in the algorithm is found to be in the calculation of remainder using complement method. The size of the remainder is always set as N - 1 bit for any combination of input. The multiplier structure is designed based on Karatsuba algorithm. Therefore, N × N bit multiplication is done by ( N - 1) bit multiplication. Numerical strength reduction is done through Karatsuba algorithm. The results show that the reduction in hardware leads to reduction in the delay.

Researchers are trying to design devices which require minimum space and power with high speed. The multipliers are the important unit in many high speed applications. But it needs more components and consumes more power. From the conventional multipliers, Bough-Wooley consumes less power but the bit length is restricted to 16 bits. For high speed devices, Wallace with Booth encoding produces good result. But Wallace will occupy more space due to the usage of more components [

In [

The MAS (Multiplier Adder Subtractor) unit is incorporated [

The problem solving techniques using Vedic Mathematics not only reduce computational time but also give the way for effective learning. In [

In [

The architecture is designed based on the combination of Karatsuba and Nikhilam sutra. in the conventional Karatsuba algorithm, the remainder is determined by taking Least Significant Half of the number without alteration. In the proposed work, the remainder is computed using Nikhilam Sutra. The detailed algorithm is given in [

Mode I―Positive Remainders

Mode II―Negative Remainders

Mode III―Mixed Remainders

Input: A, B

Output: P

Step 1: Considering A and B are N bit numbers and having positive remainders (i.e. both are greater than 2^{N}^{−1}). The positive remainders are derived by considering the numbers without MSB having N − 1 bits. (Considering A_{r} and B_{r})

Step 2: Multiplying the remainders A_{r} and B_{r}. i.e.

Step 3: Shifting the input A left side by N − 1 times. (

Step 4: Shifting the remainder of B, B_{r} by N − 1 times (

Step 5: Adding all the components to derive the final product

The proposed architecture for positive remainders is shown in

In [

Input: A, B

Output: P

Step 1: Considering A and B are having negative remainders. (i.e. both are less than 2^{N}^{−1}). The remainder is computed by complementing A & B with N − 1 bits. (Consider A_{r} and B_{r}).

Step 2: Multiplying the remainders A_{r} and B_{r}. i.e.

Step 3: Shifting the input A left side by N − 1 times (

Step 4: Shifting the remainder of B, B_{r} by N − 1 times (

Step 5: Adding all the components to derive the final product

The architecture for negative remainders is shown in

Input: A, B

Output: P

Step 1: Considering A and B are having mixed remainders (i.e. one is positive remainder and the other is negative remainder). The positive remainder is derived as per Mode I and the negative remainder is calculated as per Mode II (consider A_{r} and B_{r}).

Step 2: Multiplying the remainders A_{r} and B_{r}. i.e.

Step 3: Shifting the input A left side by N − 1 times (

Step 4: Shifting the remainder of B, B_{r} by N − 1 times (_{3} depends on the type of remainder B_{r}.

Step 5: Adding all the components to derive the product

The architecture for mixed remainder is shown in

The input multiplexer is used here to derive the remainder. Based on MSB value of A and B, the remainder is calculated. For negative remainder, the complement of A is taken. For the positive remainder, the number is taken directly considering N − 1 bits. The multiplier unit is used to multiply the remainder terms_{1} is derived by shifting the value of A by N − 1 bits. (i.e._{4} is the term that represents the multiplication of_{2}). If B_{N}_{−1} = 1, the remainder will be negative, adder/subtractor will perform subtraction operation. If B_{N}_{−1} = 0, it will perform addition operation.

The combined structure is shown in

The various conventional multipliers are considered and compared with proposed multiplier. The computational delay for various multipliers is listed in

In this paper, a new multiplication algorithm using Nikhilam sutra is presented. The modification of binary Vedic multiplier with the previous papers is presented here. In the calculation of remainder, a single bit is reduced, and hence usage of components will be reduced. Therefore, the interconnection delay and computation time are reduced. The speed and the area are optimized using this modified Vedic multiplier. The performance of the modified multiplier varies on the type of multiplier used. Finally successive approximation of proposed algorithm is also done here. Comparing with conventional methods, the combination of multiplier with Wallace multiplier gives reduced stage delay. But this combination consumes more power. Normally, Vedic multiplier is used to perform the operation with minimum delay. Therefore, in combination with conventional Vedic multiplier the proposed method gives better result. For high speed applications, proposed method with Wallace multiplier can be used. For low power and low area applications, proposed multiplier with Vedic (Urdhava) or Braun multiplier can be used. From the results it is clear that the proposed algorithm is best suited for high speed

Methods | Delay in nS | |||
---|---|---|---|---|

4 Bit | 8 Bit | 16 Bit | 32 Bit | |

Array Multiplier | 15.269 | 31.111 | 62.437 | 123.387 |

Vedic-Array | 9.02 | 29.542 | 54.871 | 99.587 |

Shift and Add Multiplier | 15.677 | 33.840 | 63.089 | 124.112 |

Vedic-SAA | 15.92 | 33.324 | 62.254 | 122.567 |

Braun Multiplier | 13.088 | 23.331 | 62.437 | 127.776 |

Vedic-Braun | 9.325 | 18.198 | 34.562 | 88.547 |

Wallace Tree Multiplier | 12.756 | 22.863 | 44.258 | 87.776 |

Vedic-Wallace | 8.57 | 18.67 | 37.478 | 94.249 |

Vedic Multiplier | 11.752 | 21.564 | 41.684 | 82.289 |

Vedic-Vedic | 8.015 | 15.234 | 21.452 | 32.584 |

Methods | Power in mW | |||
---|---|---|---|---|

4 Bit | 8 Bit | 16 Bit | 32 Bit | |

Array Multiplier | 298 | 312 | 368 | 440 |

Vedic-Array | 122 | 259 | 485 | 621 |

Shift and Add Multiplier | 310 | 368 | 501 | 636 |

Vedic-SAA | 172 | 356 | 503 | 694 |

Braun Multiplier | 113 | 149 | 406 | 706 |

Vedic-Braun | 128 | 138 | 232 | 238 |

Wallace Tree Multiplier | 113 | 154 | 375 | 706 |

Vedic-Wallace | 111 | 145 | 347 | 674 |

Vedic Multiplier | 123 | 142 | 250 | 489 |

Vedic-Vedic | 119 | 130 | 212 | 443 |

Methods | Delay in nS | |||
---|---|---|---|---|

4 Bit | 8 Bit | 16 Bit | 32 Bit | |

Array Multiplier | 15.269 | 31.111 | 62.437 | 123.387 |

Shift and Add Multiplier | 15.677 | 33.840 | 63.089 | 124.112 |

Braun Multiplier | 13.088 | 23.331 | 62.437 | 127.776 |

Wallace Tree Multiplier | 12.756 | 22.863 | 44.258 | 87.776 |

Proposed Multiplier | 8.021 | 14.654 | 21.475 | 30.542 |

and compact applications.

M. Nisha Angeline,S. Valarmathy, (2016) Implementation of N-Bit Binary Multiplication Using N - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method. Circuits and Systems,07,2332-2338. doi: 10.4236/cs.2016.79203