In this paper, a Binary Coded Decimal (BCD) topology of modular multilevel inverter with reduced component count is proposed. For the control of this inverter, hybrid control strategy is used. The proposed modular multilevel inverter uses asymmetrical dc sources and reduced number of switches topology. This hybrid modulation technique uses the multicarrier based Pulse Width Modulation (PWM) and the fundamental frequency modulation strategy. The hybrid modulation algorithm is implemented with “NUC140” micro-controller. In comparison with the conventional and some of the recently reported inverter topologies, the proposed inverter topology is able to generate high number of voltage levels in the output by using minimum number of components such as dc sources, power switches and driver circuits. This inverter offers significant performance with less number of components. The feasibility of the proposed topology is confirmed by simulation and experimental results.
A Multilevel Inverter (MLI) is an array of power semiconductor switches. It has gained increasing attention in industry and research since it was introduced in the 1980s [
There are three types of commonly used MLI topologies: Neutral point or diode clamped (NPC) [
The power quality of the MLI depends on the number of levels in the output. The main disadvantage of MLI is the requirement of more number of power switches and associated driver circuits with the increase in the number of levels at the output. This increases the circuit complexity and the overall cost and size of the system. Creation of asymmetrical dc sources is another challenge of MLI. With hybrid renewable energy generation, various voltage levels produced by different energy sources can be used as the dc sources of asymmetrical MLI. It avoids the use of flying capacitors or boost converters stage of the conventional hybrid energy generation system. To conquer these disadvantages, many topologies are introduced with reduced number of switches [
The modulation technique used to generate the gating signals is very vital to attain high performance control in the MLIs. Various modulation techniques have been introduced to improve the performance of the MLIs [
In this paper, a BCD topology of modular multilevel inverter with unequal dc sources and reduced number of switches is proposed. The performance of the proposed inverter is controlled by the hybrid control strategy. This topology requires lesser number of power switches, power diodes and associated driver circuits than the conventional topologies. These advantages are proved by comparing the proposed topology with the conventional symmetric and various asymmetric optimal topologies reported in the literature. The power loss and conversion efficiency are estimated from the simulation results. Finally, the experimental results of a 9-level inverter are presented and these validate all the theoretically obtained results.
The polarity generator is a simple full H-bridge (HBM) which provides the positive and negative polarities to the output of the level generator alternatively, so that the alternating output voltage is obtained. Switches SH1 and SH2 are turned ON and SH3 and SH4 are turned OFF during the positive half cycle while switches SH3 and SH4 are turned ON and SH1 and SH2 are turned OFF during the negative half cycle. The switches in this polarity generation part are operated at the fundamental (line) frequency.
Each sub-module in the level generation part can generate one positive level and zero level output voltage. “m” numbers of dc sources are required for “N” levels in the output of the inverter,
Number of sub-modules (n) required is given by,
Parameter | Value |
---|---|
No. of Levels | 9 |
No. of Sub-Modules | 2 |
Input dc Sources | 3 |
No. of Switches | 8 |
Load | 50Ω |
Level | Output Voltage | Magnitude Generator Sa1 Sb1 Sa2 Sb2 | Polarity Generator SH1 SH2 SH3 SH4 |
---|---|---|---|
1 | 4Vdc | 1010 | 1100 |
2 | 3Vdc | 0110 | 1100 |
3 | 4Vdc | 1001 | 1100 |
4 | Vdc | 0101 | 1100 |
5 | 0 | xxxx | 1010/0101 |
6 | Vdc | 0101 | 0011 |
7 | 2Vdc | 1001 | 0011 |
8 | 3Vdc | 0110 | 0011 |
9 | 4Vdc | 1010 | 0011 |
Maximum output voltage obtainable is,
where, Vdc is the dc source voltage.
Number of power switches (Nsw) required for a single phase inverter is,
Number of driver circuits required is,
In the proposed 9-level inverter, four levels of positive output voltage are generated by the level generator part. As the switch Sb of each sub modules (SM1 & SM2) conducts, the output voltage level of Vdc is obtained. As the switches Sa of SM1 and Sb of SM2 are operated, the output voltage level becomes 2Vdc. For the output voltage level of 3Vdc, the switches Sb of SM1 and Sa of SM2 are triggered and for the output voltage level of 4Vdc, the switches Sa of each sub modules are triggered. By properly controlling the ON and OFF states of the switches in the H-bridge module, the four-level unidirectional output voltage waveform is converted into bidirectional eight-level output voltage waveform. The zero level output voltage is achieved by turning ON the switches SH1 and SH3 or SH2 and SH4.
To generate high quality output with MLI, various modulation techniques are used. Out of these techniques, SHE or CBPWM techniques are commonly used because of ease of controllability. With fundamental frequency modulation, each switch has to be turned ON and OFF once per cycle of the fundamental frequency output. This fundamental frequency modulation provides minimal switching loss, but the harmonic contents at the output voltage become high. The quality of the output is enhanced in the CBPWM techniques, but the switching losses and the circuit complexity are increased.
The idea behind this hybrid control strategy is to combine the advantages of both the fundamental frequency modulation and the CBPWM. In fundamental frequency modulation, one carrier signal and one reference signal are used. These signals are compared and produce the switching pulses at fundamental frequency. In CBPWM, phase disposition PWM (PDPWM) is more popular. THD content is much lesser with PDPWM control strategy based MLI. In this paper, a unipolar phase disposition PWM (UPDPWM) is considered as the number of carriers required in the UPDPWM is half of the carriers required by the PDPWM. In this modulation technique, the switches in the polarity generation part are operated at the fundamental frequency and the switches in the level generation part are operated by the UPDPWM.
A basic comparator is used for the fundamental frequency PWM generation. The modulating sine waveform at fundamental frequency is compared with the zero reference and produces the pulses at the fundamental frequency. These pulses are processed by the combinational logic formed by (6)-(9). The pulses produced by the combinational logic circuit are used to control the switches in the polarity generation part of the proposed inverter.
where, GH1, GH2, GH3, GH4 are the gating pulses applied to the switches H1, H2, H3 and H4 in the polarity generation part. S1, S2, S3, S4 are the pulses produced by the fundamental frequency PWM generation part. P1, P2, P3 and P4 are the pulses produced by the UPDPWM generation part.
The modulating and high frequency carrier signals used for UPDPWM are shown in
Parameter | Value |
---|---|
No. of Carriers | 4 |
No. of Reference signals | 1 |
Modulation index for frequency | 26 |
Modulation index for amplitude | 1.05 |
Fundametal Frequency | 50 Hz |
where, Ga1, Gb1, are the gating pulses applied to the switches in the first sub-module (SM1). Ga2, Gb2 are the gating pulses applied to the switches in the second sub-module (SM2).
In order to study, the feasibility of the proposed BCD topology of multilevel inverter with hybrid control strategy, simulations were carried out using MATLAB/Simulink. The developed Simulink model for the proposed topology is shown in
In order to explore the capability of the suggested topology, the proposed inverter was compared with various types of MLIs such as symmetric CHB, asymmetric CHB and some of the topologies of asymmetrical MLI with reduced number of switches reported in the literature [
Converter Type | CHB | Topology in [ | Topology in [ | Proposed topology | ||
---|---|---|---|---|---|---|
Symmetric | Binary | Ternary | ||||
No. of Levels | 2n + 1 | 2(n+1) − 1 | 3n | 2(n+3) − 5 | 3´2(n+1) − 7 | 2n + 1 |
Switches | 4n | 4n | 4n | 5n + 6 | 6n | 2(n − 1) + 4 |
Gate Drivers | 4n | 4n | 4n | 5n + 6 | 6n | 2(n − 1) + 4 |
Diodes | 4n | 4n | 4n | 5n + 6 | 6n | 2(n − 1) + 4 |
DC Supplies | n | n | n | 3n + 1 | 2n | n |
Control Signals | 4n | 4n | 4n | 5n + 6 | 6n | 2(n − 1) + 4 |
Max. output voltage | n | 2(n+2) − 3 | 3 × 2n − 4 |
The numbers of sub-modules used in various topologies are shown in
In the proposed 9-level inverter, the number of on-state switches at any instance of operation is only four switches (two from polarity generation part and two from level generation part). This is less than the topologies presented in [
This section is arranged to evaluate the losses of the multilevel inverters. There are three types of losses incurred in the multilevel inverters: Conduction losses (when the switch is in ON state), switching losses (when the state of the switch changes from ON to OFF or vice versa) and losses due to leakage current (when the switch is in OFF state). Since the leakage current during the OFF state or blocking state is practically negligible, the losses due to leakage current are also negligible. Therefore, in the present work the losses due to conduction (Pcon) and switching (Psw) alone are considered for the power loss calculation.
In order to calculate the conduction losses, it is necessary to evaluate the losses of one typical switch and then, the similar approach could be generalized to overall system. Each power semiconductor switch is composed of a MOSFET and anti-parallel diode. To identify instantaneous values of conduction losses, the following Equations [
VT and RT are on-state voltage and the resistance of the MOSFET respectively. β is a constant dependent on the MOSFET characteristics. VD and RD are on-state voltage and the resistance of the diode respectively. To calculate the conduction losses, it is required to specify the number of MOSFETs, NT(t), and diodes, ND(t), existing in the current mode of operation. It is clear that the number of on-state switches is dependent on the current mode of operation and time-variant. The average of the conduction losses is calculated by,
To evaluate the switching losses, the linear approximation of the current and voltage during switching periods is considered. Based on these assumptions, the energy losses during the turn-on period of power switch are calculated by [
where, Eon,J is the turn-on loss of the Jth switch; ton,J is the turn on time of the Jth switch and I is the current through the switch after turning on.
The total switching loss depends on the number of switching per cycle. The average switching loss (Psw) can be evaluated by,
where, f is the fundamental (line) frequency; Non,J and Noff,J are the number of turn-on and turn-off of the Jth switch during one half cycle of the fundamental frequency. Eon,Ji and Eoff,Ji are the energy losses of the Jth switch during ith turn-on and turn-off respectively.
The total loss (Pt) of the inverter is calculated by,
Once the total loss is determined, the relative inverter efficiency of the inverter is calculated by,
To evaluate the output voltage waveform quality, the values of total harmonic distortion (THD) are calculated as suggested in the IEEE standard 519. THD of the output voltage can be evaluated by,
where, V1 and Vn are the fundamental component and harmonic component of the output voltage.
The value of weighted total harmonic distortion (WTHD) can be evaluated by,
To verify the achievability of the proposed BCD topology, a hardware set-up was fabricated for a 9-level inverter with hybrid control strategy.
In this work, BCD topology based modular multilevel inverter with hybrid control strategy was successfully de-
Mf | Ma | %THD | %WTHD | Vo1 in pu | Pt in pu | %η |
---|---|---|---|---|---|---|
26 | 1.1 | 11.22 | 0.883 | 1.05 | 0.113 | 88.72 |
26 | 1.05 | 10.9 | 0.779 | 1.06 | 0.151 | 84.9 |
26 | 1 | 12.05 | 0.694 | 1.002 | 0.198 | 80.23 |
26 | 0.95 | 14.6 | 0.596 | 0.95 | 0.279 | 72.15 |
26 | 0.9 | 15.38 | 0.648 | 0.9 | 0.352 | 64.82 |
26 | 0.85 | 16.05 | 0.615 | 0.86 | 0.414 | 58.59 |
26 | 0.8 | 16.5 | 0.594 | 0.8 | 0.49 | 50.96 |
Modulation Technique | %THD | Vo1 in pu |
---|---|---|
Presented in [ | 14.5 | 1.00 |
Presented in [ | 12.66 | 1.09 |
Phase opposition disposition PWM | 12.9 | 1.01 |
Hybrid control strategy | 10.9 | 1.06 |
Parameter | Value |
---|---|
No. of Levels | 9 |
Input DC Sources | V1 = V2 = 5 V, V3 = 10 V |
No. of Switches | 8 |
Type of switch | MOSFET (IRF540) |
Type of controller | ARM® CortexTM-M0 NUC140 |
veloped. To demonstrate the superiority of the proposed topology, several comparisons were made between the developed proposed inverter topology and the other topologies that the literature cites. From the comparisons it could be seen that the proposed topology required less number of power switches, driver circuits, and dc sources than the topologies reported in the literature. The proposed inverter topology needed minimum number of components, could promise better performance, reliability, efficiency and reduction in cost and size of the inverter when we went for the higher number of output levels. Finally, the performance of the proposed inverter with hybrid control strategy was demonstrated with the experimental results obtained through a 9-level inverter.
Vasudevan Karthikeyan,gopal Jamuna, (2016) Hybrid Control Strategy for BCD Topology Based Modular Multilevel Inverter. Circuits and Systems,07,1441-1454. doi: 10.4236/cs.2016.78126