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The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock frequencies and very low supply voltages. Though the traditional self biased PLL is still being widely used with hardly any modification, it is becoming imperative to take a relook at the design aspects of these PLLs with respect to their jitter performance. This paper presents a systematic simulation study of designing the self biased PLL with the goal of reducing jitter. It further shows that if the self biased PLL is adapted into a dual loop scheme in a systematic manner, a significant jitter improvement can be obtained. Detailed simulations carried out in 0.18 μm CMOS technology indicate a reduction of 56% or more in jitter for the systematically designed dual loop scheme in comparison to the jitter reduced traditional self biased PLL.

The well proven self biased adaptive bandwidth PLL [

However in today’s scenario of tiled and multi core processers, this well proven PLL architecture operates in an environment of rapidly and widely varying combinations of clock frequencies and (low) supply voltages. This is needed in order to meet the overall power envelope constraints [

In this work, a systematic design of these self biased PLLs for jitter reduction is described. The crucial functional blocks that decide the jitter performance, namely the charge pump and the VCO are designed in such a way that the overall jitter contribution is reduced. This design methodology is further extended to a self biased PLL incorporating dual loop scheme to attain significant jitter performance improvement.

Though there have been many papers appearing periodically in the literature addressing the issue of jitter reduction in PLLs, very few of these are in the context of self biased PLLs. In [

Dual loop techniques using conventional oscillators have recently been proposed in [

The present paper is organized as follows. Section 2 explains the design procedure of the self biased PLL with emphasis on jitter reduction. Detailed simulation results and overall system performance are presented in Section 3 and the conclusions of the present work are given in Section 4.

The block diagram of the traditional self biased PLL [_{1}), Loop Filter (LPF), VCO and a Prescalar. It also includes a Bias Generator (BG) to provide bias currents to the charge pump, the PFD as well as the VCO, and this bias current generated adaptively, tracks the operating frequency. The VCO employed is a ring oscillator, and its delay element uses a linearized resistive load enabling the PLL to operate over a wide range of frequencies.

The jitter performance of the traditional self biased PLL can be normally studied by considering the Noise Transfer Functions (NTFs) and the noise Power Spectral Densities (PSDs) of the various functional blocks of the

PLL. The overall PLL output noise PSD

In the above expression, H_{CP}, H_{LPF}, H_{VCO} and H_{DIV} represent the NTFs of the blocks CP_{1}, LPF, VCO and Prescalar blocks respectively (

the corresponding noise sources. The expressions for the NTFs of the various functional blocks as described in [

In the above expressions, I_{cp} represents the charge pump bias current and N represents the Prescalar divider ratio. _{VCO}, I_{cp}, and the loop filter cutoff frequency, it is well known [_{cp} and K_{VCO} [_{n} and damping constant ζ given by

Given all the above dependencies, the selection of optimum values of K_{VCO} and I_{cp} for minimizing overall jitter is a non trivial task. Further minimizing overall jitter implies reducing the noise PSDs as well as the NTFs of the various blocks.

Taking up the case of NTFs first, a careful consideration of all the dependencies leads to the following set of assumptions/observations which can aid in the systematic design of a low jitter self biased PLL.

1) Since the original PLL is wideband, it is assumed that the dominant contributor to the overall jitter is the noise originating from the charge pump [

2) A reduction in K_{VCO} leads to a reduction in the charge pump contribution to overall jitter [

3) While reducing K_{VCO}, due consideration must be given to the fact that other factors that are related to it through the PLL loop equations could mitigate the possible improvement in jitter.

4) One possibility for reducing jitter is to reduce K_{VCO} without altering the denominators in (1), and this can be accomplished with a corresponding increase in I_{cp}. This approach is followed in [_{VCO} cannot be reduced below a certain limit.

5) Alternatively, one can reduce K_{VCO} and also alter the denominator in (1), which in turn would imply that the system would operate with altered loop parameter values of ω_{n} and ζ. In return for a reduction in overall jitter, these loop parameters can be altered to the extent that the conditions of PLL loop stability and lock time are not degraded significantly. This is the approach followed in the present work and is iteratively designed through simulation so that the reduced jitter does not degrades settling time performance.

Next, taking up the case of the reduction of the noise PSDs of the individual blocks, the dominant noise sources within the key blocks like charge pump and the VCO have to be identified, and then suitably altered to the extant permissible without disturbing the PLL loop dynamics. Considering the VCO first, the circuit diagram of the delay element employed in the self biased PLL [_{4}-M_{7}) and switch transistors (M_{2}-M_{3}), the tail transistor M_{1} is generally considered to have negligible impact on the overall jitter [_{2}-M_{7}) have to be chosen such that the VCO noise PSD is reduced while meeting the operating frequency range and VCO gain K_{VCO}. VCO gain of the symmetric load VCO as derived in [_{4} or M_{7}. C_{eff} represents the effective capacitance that determines oscillator frequency.

The circuit diagram of the charge pump employed in the self biased PLL is as shown in _{7}-M_{14}) and switch transistors (M_{3}-M_{6}).

The dimensions of all the jitter sensitive transistors (M_{2}-M_{7} of _{3}-M_{14}, of _{VCO} and bias currents in the charge pump). But a unique feature in self biased PLL is that the charge pump device dimensions are derived using the delay element device dimensions [

For the traditional self biased PLL, the above mentioned considerations about NTFs and the noise PSDs of the various functional blocks will enable one to (a) size the devices in charge pump and VCO to minimize device noise contribution to jitter and (b) systematically reduce the K_{VCO} and study its impact on jitter. The quantitative results based on simulations will be presented in the next section.

While considering the reduction of K_{VCO}, one cannot reduce K_{VCO} without compromising the capture range and settling time of the traditional self biased PLL. Hence the dual loop scheme [_{VCO} without any trade off with capture range and settling time. The principle based on which the traditional single loop self biased PLL is modified into a dual loop scheme to reduce K_{VCO} is briefly discussed next.

The complete block diagram of the dual loop scheme is shown in _{1} and CP_{2}, and a bias generator BG_{1}. The charge pump block CP_{2} in the FLL is used to emulate the resistance in LPF.

The PLL part in the dual loop scheme comprises of the PFD, charge pump CP_{3}, an LPF and a bias generator BG_{2}. The bias current of CP_{3} is derived from the bias generator BG_{2}. The bias voltages from BG_{1} and BG_{2}, V_{bn_FLL} and V_{bn_PLL} respectively are combined in a half buffer replica stage to generate the bias voltage V_{bp} for the ring oscillator.

The FLL acquires and brings the output frequency to within the PLL’s capture range. While the FLL tracks the reference frequency, the PLL is disabled by a digital control circuit, and is later enabled when the frequency falls within its capture range. Therefore, under phase lock and very close to phase lock, the entire dual loop system operates only with the PLL being active, and the system reduces to a conventional self biased PLL with a reduced VCO conversion gain.

As was done above the single loop case, the dual loop scheme’s device dimensions of VCO and CP of the PLL part of loop are chosen so as to minimize the respective noise PSDs while satisfying the respective block level specifications. The jitter performance of this systematically designed dual loop is compared with the systematically designed traditional self biased PLL and the results are discussed in the following section.

All circuit simulations have been carried out using UMC 0.18 μm CMOS technology process libraries. The simulation results are presented in the following order. First, the traditional self biased PLL was designed with the optimum device dimensions of VCO and charge pump functional blocks determined using PNoise analysis in Cadence for reduced jitter performance. The choice of the optimum device dimensions from the PNoise plot is

discussed. Next, the extant of possible improvement in the jitter performance obtained by systematically reducing K_{VCO} of the traditional self biased PLL, is presented. Based on this, the K_{VCO} of the VCO in the PLL is set and accordingly the dual loop self biased PLL is designed. The functionality of the dual loop scheme is verified and the capture transients are presented. The jitter performance of the dual loop is then compared with the jitter reduced traditional self biased PLL employing a high K_{VCO} for the required capture range.

The traditional self biased PLL was designed with the loop parameters ω_{n}/ω_{ref} as 1/15 and ζ chosen as 1 respectively. The bias generator was designed for a linear operating range of 0.3 V to 1.1 V that provides control voltage to VCO. For a VCO tuning range of 200 MHz to 3 GHz, K_{VCO} is computed to be 3.5 GHz/V. Based on the K_{VCO} expression given in (6) the ratio of device dimensions of M_{4-7} to C_{eff} is defined as given below.

With C_{eff} chosen as 210 fF, the constraint on dimensions (W/L)_{M}_{4-7} is set as given below.

Based on chosen C_{eff}, the above constraint defines the device dimensions for (W/L)_{M}_{2-3} as 6/0.18 since capacitance of (W/L)_{M}_{4-7} and (W/L)_{M}_{2-3} together contributes C_{eff}.

The device dimensions of switch transistors (W/L)_{M}_{2-3} and symmetric load transistors (W/L)_{M}_{4-7} can be increased from the given constraint of (9)-(10) while satisfying the ratio required to meet the K_{VCO} value. Increasing device dimensions increases C_{eff}. Hence increasing the device dimensions beyond a range will affect its highest operating frequency. Thus the upper limit on the possible device dimensions that satisfies the operating frequency range is given by the constraint below.

The permissible values of device dimensions of (W/L)_{M}_{2-3} and (W/L)_{M}_{4-7}, that satisfies K_{VCO} and operating frequency range are given as below

Choosing from these range of device dimensions, there VCO gain characteristics are plotted and are shown in

Device dimension of M_{1} of the delay element is chosen for the required bias current. At the highest frequency of operation the maximum bias current was computed to be 200 μA dependent on the gain and band width value decided in the bias generator. Dependent on this bias current and the respective bias voltage V_{bn}, the device dimension (W/L) of the tail transistor M_{1} is computed to be 32/1.

Since the charge pump circuit in the traditional self biased PLL is a replica of the delay element architecture. Therefore for every feasible set of device dimensions in VCO, there is a related device dimension set for the charge pump circuit, which is appropriately scaled by the factor x by which the charge pump current of the self biased PLL is derived from the delay element bias current as described in [_{n}/ω_{ref} as 1/15. The permissible range of device dimensions of charge pump circuit thus obtained is given below

In _{2}-M_{7} (of

Similarly, in _{7-14} with minimum transconductance g_{m}, the output noise current PSD is smallest.

It was observed through simulations that the device sizes corresponding to the plot labeled 1 in

Considering the choice of reduced K_{VCO}, its impact on jitter performance was analyzed by simulating the traditional self biased PLL of dual loop system using VCOs with different K_{VCO} settings but with device dimensions (obtained from PNoise plot) that presents minimum noise PSDs. The jitter performance results are given below in _{VCO} is reduced. This follows with the fact that as K_{VCO} is reduced by certain factor, the impact of systematic noise on output phase noise is also reduced by the same factor. From the different values tabulated, K_{VCO} of 467 MHz/V was chosen for the design of dual loop PLL.

Next, in order to compare the jitter performances of the dual and traditional self biased PLLs, the eye diagram for both cases are plotted in

Two deviations need to be pointed out this stage. First, a K_{VCO} setting of 467 MHz/V is used as against the lowest possible K_{VCO} of 340 MHz/V as given in

A summary of the performance of the present work is provided in

K_{VCO} (MHz/V) | RMS jitter (pS) | K_{VCO} reduction factor M | Jitter reduction (compared with K_{VCO} = 3600 MHz/V case) |
---|---|---|---|

3600 | 2.27 | 1 | 1 |

1450 | 1.04 | 2.5 | 2.2 |

1000 | 0.94 | 3.6 | 2.4 |

630 | 0.49 | 5.7 | 4.6 |

540 | 0.43 | 6.6 | 5.3 |

467 | 0.30 | 7.7 | 7.6 |

340 | 0.22 | 10.5 | 10.3 |

This work | Result reported in [ | Result reported in [ | Result reported in [ | ||
---|---|---|---|---|---|

Traditional self biased PLL | Dual loop self biased PLL | ||||

Output frequency (MHz) | 2720 | 2720 | 3100 | 2100 | 700 |

Reference (MHz) | 170 | 170 | 108 | 65.6 | 1 |

Tuning range (GHz) | 0.8 - 3.2 | 0.8 - 2.8 | 1.4 - 3.2 | 0.86 - 2.1 | - |

K_{VCO} (MHz/V) | 3600 | 470 | 10 | - | 350 |

Lock time (frequency step) | 0.16 μS (1.4 GHz) | <1 μS (710 MHz) | 85 μS (940 MHz) | <3 μS (1.3 GHz) | - |

RMS jitter (pS) | 1.6 (0.0043UI) | 0.8 (0.0022UI) | 1.01 (0.0031UI) | 1.37 (0.0028UI) | 1.32 (0.0009UI) |

Power (mW) | 35.0 | 35.8 | 27.5 | 5.3 | - |

FOM (dB) (as in [ | −220.7 | −226.8 | −225.5 | −230 | - |

Supply voltage | 1.8 | 1.8 | 1.2 | 1.8 | - |

Technology (nm CMOS) | 180 | 180 | 65 | 180 | - |

In terms of jitter and _{VCO} would also have shown comparable jitter performance but with settling time greater than 1 µs.

This paper presents a systematic procedure for designing a low jitter self biased PLL based on simulation results. Noise generated from the individual functional blocks was analyzed, and a method was proposed to choose the circuit parameters for jitter reduction. The jitter improvement factor obtained by using a reduced K_{VCO} was determined experimentally through simulation. Two conclusions can be drawn from this simulation study. First is that, in the traditional self biased PLL, the minimum jitter is observed, by using device dimensions that reduce noise PSD from the charge pump and not from the VCO. This leads to the first conclusions that in wide bandwidth PLL, the significant noise contributor is the charge pump circuit. Second is that with K_{VCO} scaled, the PLL bandwidth becomes narrower; the VCO phase noise contribution to the overall phase noise has to increase; and the jitter improvement obtained can be mitigated. Even under this narrow bandwidth condition, a significant jitter performance improvement is observed. Hence it can be concluded that the dominant noise contributor is the charge pump systematic noise, and is observed to get scaled down by the same factor by which the K_{VCO} is reduced. The dual loop technique thus implemented with reduced K_{VCO} shows significant jitter reduction. Although comparison of the present work with silicon implementation results may not be entirely fair, in terms of jitter, lock time and FOM, it was shown that the systematically designed dual loop system performance is either better or comparable to the recently reported work on a ring oscillator based dual loop PLL [

J. Dhurga Devi, (2016) Jitter Reduced Self Biased PLLs—A Systematic Simulation Study. Circuits and Systems,07,533-542. doi: 10.4236/cs.2016.75045