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This paper proposes a triple output converter with buck, boost and inverted outputs and controlled through duty cycle estimation. In the existing converter, to generate the negative output, the power flows from load to the supply (from the boost output to the supply) during a part of the cycle, which increases cycle time and losses, and reduces the power level. To overcome this, a modified converter with a main and an auxiliary inductance and with reduced number of switches is proposed. The converter can operate in continuous and discontinuous conduction modes and the outputs can be independently controlled. An analysis of the converter is done for both modes. A simplified control of the converter through duty cycle estimation is suggested to regulate the outputs, which does not have the constraint that the current ripple has to be small. The control works both in the continuous and discontinuous modes. The simulation results closely match with the analysis. A prototype of the converter is constructed with a Spartan FPGA system and results have been presented.

Multi-output DC-DC converters have become very popular recently and they are particularly used in many portable and handheld consumer applications. Portable devices use sub-modules which have different voltage requirements. Their small-size and light-weight make them very attractive and the cost is also optimized. Traditionally, isolated transformer-based multi-output DC-DC converters were widely employed to provide multiple output voltages. However, they are relatively bulky due to the presence of the reactive components. The single- inductor multi-output DC-DC converters were developed to effectively reduce the hardware required for providing multiple output voltages. The converters provide more than one output while requiring only one inductor and this helps in saving board space and reducing the overall cost. Multi-output converters apart from requiring buck and boost outputs also sometimes require a negative supply voltage as in an OLED display panel application. Hence it becomes necessary that the single converter supplies all the three types of voltages, step-down, step-up and a negative output simultaneously. Various such configurations have been discussed in literature [

The inductor is initially charged by making S_{0} ON. When S_{0} is opened, S_{1} is closed and the inductor charges the boost output V_{1}. The inductor current is allowed to become zero after which the boost output charges the inductor in the opposite direction through the body diode of the switch S_{1} and through the supply. Thus power is returned back to the supply for the sake of charging the inductor in the reverse direction. When the switch S_{1} is opened, S_{2} is closed and the stored energy in the inductor is partly transferred to the negative output V_{2}. When S_{2} is opened, S_{3} is closed and power is transferred to the buck output V_{3} through the inductor L. This converter while providing all the three types of outputs has the problem that there is a reverse power flow from the load to the supply to generate the inverted output. This increases the ripple since the current has to pass through zero, twice in a cycle. The cycle time and losses are also increased.

The problems mentioned above are overcome in the proposed converter with reduced number of switches as shown in _{1} and L_{2} in the proposed converter. V_{1} is the boost output, V_{2} is the inverted output and V_{3} is the buck output. C_{1}, C_{2}, and C_{3} are the output filter capacitors to the outputs V_{1}, V_{2}, and V_{3}, respectively, where R_{1}, R_{2} and R_{3} are the corresponding loads. These three outputs are achieved by using two inductors (L_{1}, L_{2}) with three switches (S_{0}, S_{1} and S_{2}). In the proposed configuration, the voltage levels of all three outputs can be adjusted by varying the duty cycles of switches S_{0}, S_{1}, and S_{2}. S_{0} is ON for the time dT_{s}, S_{1} is ON for the time d_{2}T_{s} and S_{2} is ON for the time d_{1}T_{s} in every cycle where T_{s} is the cycle time period. The inductor L_{1} is charged through switch S_{0} during dT_{s} and simultaneously L_{2} and the buck output is powered through switch S_{2} for duration of d_{1}T_{s}. Once S_{0} is turned OFF, D1 turns ON to drive the inverted output (V_{2}) for the rest of the cycle if V_{2} is operating in continuous conduction mode. When switch S_{2} is turned off, S_{1} is turned ON to store additional energy required by the boost output in the inductor for duration of d_{2}T_{s}. When S_{1} is turned off, the stored energy in the inductor L_{2} is transferred to the boost output V_{1} through diode D_{3} for the balance duration d_{3}T_{s}.

If the converter is operating in discontinuous conduction mode, the cycle repeats after a dead time. For operation in continuous conduction mode, the inductor current reaches its steady-state minimum value at the end of d_{3}T_{s}. There are five modes of operation in the converter. The inductor current waveforms are shown in

The equivalent circuits during the modes are shown in Figures 4(a)-(d).

Initially, at the beginning of the cycle, the switches S_{0} and S_{2} are turned ON and the inductors L_{1} and L_{2} are charged simultaneously for duration of dT_{s} and d_{1}T_{s} respectively. During the charging of the inductor L_{2}, the buck output is also simultaneously fed power.

In mode 2, the switch S_{0} is turned OFF and the diode D_{1} becomes forward biased and starts conducting. The energy stored in the inductor L_{1} is discharged through D_{1} (i.e. the current flows from inductor L_{1} through D_{1}) to drive the inverted output for the balance duration in the cycle.

In this mode, the switch S_{2} is turned OFF when the requirement of buck output is met. The switch S_{1} is turned ON to further charge inductor L_{2} since the boost output may require more energy than what is already stored in the inductor L_{2} to produce the required output voltage.

When switch S_{1} is turned OFF, the stored energy in the inductor L_{2} is completely transferred to the boost output through diode D_{3} till the current becomes zero.

After a dead time given by

The modes of operation for the continuous conduction mode are similar to the above with the difference that

that the current starts from a value of “m” in the beginning of the cycle and at the end of the cycle, it again reaches “m” (at steady state). The inductor current waveforms are shown in

During Mode 1, from volt-second balance of inductor L_{2},

, (1.1)

From capacitor charge-balance considerations,

During Mode 2, the inductor current rises from “m” to “n”. Applying volt-second balance

During Mode 3, the current falls from “n” to zero. Applying volt-second balance for the inductor L_{2},

Applying charge balance consideration to the boost output,

For discontinuous conduction mode operation, the dead time gives an additional degree of freedom which helps to achieve a unique solution. If the dead time is chosen as 5%, the sum of the three duty cycles d_{1}, d_{2} and d_{3} would be 0.95 which is a required design equation.

Since _{1}”, “d_{2}”, “d_{3}”, “m”, “n” and “a” and six equations from (1.1) to (1.6). Hence an unique solution can be obtained. Knowing “a” and choosing T_{s}, L_{2} can be obtained. The negative output is from a buck-boost converter whose output voltage (for continuous conduction) is

The inductor value L_{1} can be obtained based on ripple considerations. Assuming a permitted inductor ripple current of “r” % of the rated current,

From volt-second balance of inductor L_{1},

From (1.7), (1.8) and (1.9),

From (1.10), L_{1} can be obtained for a permitted ripple “r”. As a design example, the specifications for a chosen converter is shown in _{2} is obtained as 20 uH. Inductance value L_{1} is found to be 141 uH. The duty cycles are found to be d_{1} = 0.535, d_{2} = 0.053 and d_{3} = 0.365.

While the buck output is supplied, the inductor is also charged along with it. The energy stored in the inductor at the end of the buck operation may not be adequate for supplying the boost output and additional charging may be required for the time duration d_{2}T_{s}. The condition for this is obtained as follows:

For d_{2} to exist, n should be greater than “m” and

From (1.4) & (1.5),

For

is the required condition, where ^{th} output^{ }.

From volt-second considerations of inductor L_{2},

From output capacitor charge balance considerations,

Circuit parameters | Values |
---|---|

Supply voltage V_{s} | 12 V |

Switching frequency | 50 KHz |

Load resistance R_{1} | 30 Ω |

Load resistance R_{2} | 10 Ω |

Load resistance R_{3} | 5 Ω |

Output voltage V_{1} | 24 V |

Output voltage V_{2} | −5 V |

Output voltage V_{3} | +5 V |

There are 7 variables, “d_{1}”, “d_{2}”, “d_{3}”, “m”, “n”, “p”, “T_{s}/L” and six equations from (1.13) to (1.18). Since there are 6 equations for 7 variables, there is no unique solution and several solutions are possible. For higher values of “m”, the average current to each output increases and ripple decreases, T_{s}/L_{2} would decrease and L_{2} would increase for particular T_{s}. The solution can be obtained from any iterative software and a typical solution for a switching frequency of 50 KHz is L_{1} as 141 µH, L_{2} as 87 µH, d_{1} as 0.52, d_{2} as 0.09 and d_{3} as 0.39. The simulation of the system was done using PSIM software with the specifications of the converter as given in

The control strategy followed in this paper is based on the approaches suggested by Zhonghan Shert et al. in [

The output of the PI voltage regulator for a particular output indicates the demanded current and this must

relate to the overall average inductor current during the period when power is discharged in to the particular buck/boost output. Using this property, the duty cycles for the different modes are estimated. The duty cycles of the different modes are predicted based on the present duty cycles and the current demand of the two outputs. The actual (valley) current at the beginning of the cycle is measured and this corresponds to the value of “m” in the equations (1.13) to (1.18) discussed above. The current “m” is typically measured with an analog-digital converter like TLC1541. Multiple current measurements are not required and only one sample is required at the beginning of a full time period. Alternatively, a current mirror concept can also be used. The buck and boost outputs are compared with their set points and the error signals are passed through PI regulators. The output of the regulators for the buck and boost outputs are denoted as

Choosing (T_{s}/L) and measuring “m”, “n” can be found. From (1.13), since “n” is found, d_{1} can be obtained as

The average inductor current during mode 2 (say “K”) can be obtained as the difference between the overall average inductor current and the sum of the average currents of the two outputs as

Combining (1.22) with (1.14), d_{2} can be obtained as

Knowing d_{1} and d_{2}, d_{3} can be found as

The algorithm for the prediction control is shown in

To highlight the fact that the predictive control also works for a large ripple, the inductance value was changed from 30 µH to 7.5 µH and for a sudden change in supply voltage between 10 and 16 V, the output voltages, duty cycles and inductor current waveforms are shown in Figures 8(h)-(i). In

The hardware implementation is done for the converter in discontinuous mode using an FPGA controller, Spartan 3E XC3S250E system working at a clock frequency of 20 MHz. The pulses generated from the FPGA controller are passed through opto-couplers 6N137 and then given to the driver TC4584BP. They are then used to switch the MOSFETs IRF 840. The hardware waveforms are given in Figures 9(a)-(e) and the hardware setup is shown in

This paper proposed an alternate converter with a main and an auxiliary inductor, capable of generating both positive and negative outputs and in both buck and boost configurations. The topology does not involve any reverse power flow to the supply and hence time periods can be shorter and higher power levels are possible. The topology is validated through simulation using PSIM software and further through hardware results obtained with a Spartan FPGA system. The suggested topology is generic and is extendable to more outputs. A novel control method through duty cycle estimation has been suggested which is capable of regulating output voltages against line and load disturbances. Since the duty cycles of the next time period are estimated in the present cycle by direct computation, the control method is capable of overcoming cross-regulation issues.

Kumaraswami Sundararaman,Mahadevan Gopalakrishnan, (2016) A Bi-Polar Triple-Output Converter with Duty Cycle Estimation. Circuits and Systems,07,198-210. doi: 10.4236/cs.2016.74019