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We propose a new approach in reducing the power consumption of the successive approximation register Analog to Digital Converter (SAR-ADC) by changing the convergence algorithm of the Digital to Analog converter (DAC) input of the SAR-ADC. Different search algorithms such as binary search tree, moving binary search tree (BST), least significant bit shifter (LSB), adaptive algorithm and split-register moving BST algorithm are designed and analyzed for faster convergence of the DAC input. In this paper, we design a 0.8 GS/s, 8 bit (Effective number of bits (ENOB)—7.42), 8.352 mW SAR ADC with a proposed moving BST algorithm in 65 nm CMOS which ranks amongst the current state of the art ADCs with a FOM 65.25 fJ/step.

Analog to digital converters (ADC) are among the most important electronic structures due to the technological shift and advances in digital electronics. There are many tradeoffs in designing ADCs including power, cost, sampling speed, resolution; the most challenges are in designing a high frequency and low power ADC. In some applications, the size of device becomes the main concern; an example would be for imaging sensors that require an ADC for each pixel of input. Successive approximation register (SAR) analog-to digital converters (ADCs) require several comparison cycles to complete one conversion, and therefore have limited operational speed [

The good thing about this parameter is that it is not dependent on the structure [

Here in this paper, we looked at a different idea of reducing the power consumption by decreasing the iterations and the time it takes for the DAC to stabilize to its input value. We propose different search algorithms for SAR-ADC and analyze the design and performance tradeoffs. We feel that this could potentially be used to design low power consumption ADCs.

Most commonly [

The regular binary search tree (

The following example illustrates the mechanism of the circuits. For instance, the two consecutive digital signals, D, are:

D [

D [

The number of conversions for the binary search to reach to the value of 609 is 9.

(10000000000 -> 1100000000 -> 1010000000 -> 1001000000 -> 1001100000 -> 1001110000 -> 1001101000 -> 1001100100 -> 1001100010 -> 1001100001)

Irrespective of what the previous signal is, the binary search always starts from the middle value 1000000000 (512). This happens to be a concern because if we come up with algorithms that take this into consideration, then much power can be saved.

In order to overcome the limitation of BST, we have proposed moving BST. The moving binary search tree starts with the previous value and compares with the actual input. If the output of the comparator (Cp) happens to be 1, then it means that the value lies between previous value and 1053; and if it is 0, then the value lies between 0 and previous value. If Cp equals 1, then the value is readjusted to (previous value + 1053/2) and the comparison is done again. This is repeated until the value equals the input value to the comparator. How can this method be better than the regular binary search tree? The number of iterations it takes for the regular binary search tree to converge to the current value is higher than the moving binary search tree because the span or the range in which the moving binary search tree searches is lower. A moving BST can be implemented using the control structure in

The following example illustrates the mechanism of the circuits. For instance, the two consecutive signals are:

D [

D [

The number of conversions for the moving binary search to reach to the value of 609 is 7.

(1001011111 -> 1101011111 -> 1011011111 -> 1001111111 -> 1001101111 -> 1001100111 -> 1001100011 -> 1001100001)

The number of conversions has reduced from 9 to 7 which reduce the power consumption. Using MATLAB it is shown that the number of iterations Moving binary search tree takes to converge to the current value from previous value is on an average 44.12% of that taken by Binary search tree algorithm (as shown in

Intermediate latch (

Range calculator consists of a difference-calculating circuit (

A general linear search method takes a longer time to converge than a BST because the big O notation is of the order of n, which is the worst of all the search algorithms. But why don’t we use the advantage of linear search? When the difference between two consecutive signals is very close, then linear search seems to be a good method to resort to. To implement the moving binary search tree which uses previous result as starting point for conversion, the proposed search tree requires to move “up or down” at any level of the tree. Therefore, a summer (block diagram in

D [

D [

The number of conversions for the adaptive algorithm (

1001011111 -> 1001100000 -> 1001100001

This happens because the consecutive signals are so close to each other that the difference between them is less than the number of bits. Hence the linear search is chosen and the value converges in 2 iterations.

This is another interesting algorithm we have proposed (

D [

D [

The number of conversions for the LSB shifter to reach to the value of 767 is 3.

(1000001100 -> 1000001101 -> 1000001111 -> 1000011111)

The Moving BST takes 6 conversions to do the same.

(1000001100 -> 1100001100 -> 1010001100 -> 1001001100 -> 1000101100 -> 1000011110 -> 1000011111). While the regular BST takes 9 conversions to do the same (1000000000 -> 1100000000 -> 1010000000 -> 1001000000 -> 1000100000 -> 1000010000 -> 1000011000 -> 1000011100 -> 1000011110 -> 1000011111)

But this is not true for all cases. There is a big limitation: Moving BST and BST will be faster if the current signal cannot be reached with “all bit flip 1” or “all bit flip 0” modifications to the previous signal or if the current signal has a difference in two consecutive bits of altering values (e.g. previous signal―0000001100 and current signal―0000010110).

The input from comparator acts as the select signal to the multiplexer shown in the circuits which changes either least significant zero/one based on the analog input to the comparator. This circuit when implemented gave a better FOM than a BST algorithm with a limitation that it gave better performance only for above mentioned input condition and it increased the area.

When the input signal is slowly varying or if the sampling rate is very high, then the current value may be close to the previous value, then why do we need to do the regular BST or moving BST for the entire range of 0 to 1023? Instead, we can do the same moving BST for a smaller range which could eventually reduce the iterations and hence power consumption. So, in this method we are planning to use 8 registers of size 128 each which give 8 boundary values (0, 128, 256... 896). For example, if the current value is 169 then moving BST is done between 128 and 255. Since the signal is slowly varying, the next value will either be in the same register or in the adjacent registers (i.e. first register (0 - 127) or second register (128 - 255) or third register (256 - 383)). Now, how does the algorithm decide which register the value is in? We store the 8 boundary conditions in a memory cell and they are selected using a multiplexer whose control is based on the comparator value. The previous value is in a register and that particular register is known to us. Now three boundary conditions are compared with the analog input, i.e. present, previous and next registers. When the comparator value is 0, it means that the value is in previous register and if it’s one, then it can be in the same or next register.

So based on these comparisons, the register of interest is selected and the moving BST is performed. Will these 8 registers increase the area to a large extent? So these 8 registers are not physical registers, they are just an imaginary assumption hence the initial thought that blocks our mind regarding increase in area is negated. Only the memory cell which stores those 8 boundary conditions is an additional component but the advantage is that, it reduces the number of iterations by 8. Now, why is that we choose 8 imaginary registers and not any other number? Again that depends on how slow the input signal is changing or how fast the sampling rate is. This algorithm is comparable to another similar approach which assumes a short span around the previous value in which it searches and expands its search area if the value is not within that span. But the only difference in this split-register algorithm is that, it finds the search area and then searches thereby saving a lot of iterations (i.e. if the current value is not very close to the previous value then there can be unwanted search iterations used). The layout of the split register module and the block diagram are shown in

The proposed algorithms are better in terms of power consumption but they would increase the area because of the complex logic structures used and the overall speed is a question which could limit the sampling rate. Hence there is a tradeoff between power, sampling rate, area and cost.

If power consumption was the only concern, then a possible approach of combining all the algorithms would be feasible. Using a range calculator and a difference calculator unit in identifying the type of input signals and the difference in consecutive signals could help in choosing which algorithm to be used. Hence a select signal can be extracted which chooses which algorithm to use for which input signal. The improvement in convergence time is shown in

References | Architecture | Process | Bits | Fs (Gs/sec) | Power (mW) | FOM (fJ/Step) |
---|---|---|---|---|---|---|

Shan [ | Pipelined | 180 nm | 8 | 0.2 | 22 | 430 |

Flynn [ | Folding-Flash | 65 nm | 6 | 0.4 | 200 | 7813 |

Yahya [ | Delay-line | 65 nm | 4 | 1 | 2 | 196 |

Chun [ | SAR | 130 nm | 10 | 0.05 | 0.826 | 29 |

Chandrakasan [ | SAR | 65 nm | 5 | 0.25 | 1.2 | 240 |

J. Yang [ | SAR | 65 nm | 6 | 1 | 6.7 | 210 |

Our work | SAR | 65 nm | 8 | 0.8 | 8.352 | 65.25 |

A new approach to low power consumption with different search algorithms and associated control logic has been proposed for the SAR ADC. The proposed modified BST SAR-ADC design chip with 8 bit at 0.8 GS/s consumes 8.532 mW of power in 65 nm CMOS which achieves a power saving of about 56% compared to that of a regular binary search tree SAR-ADC.

AnanthanarayananParthasarathy, (2015) An 8 Bit 0.8 GS/s 8.352 mW Modified Successive Approximation Register Based Analog to Digital Converter in 65 nm CMOS. Circuits and Systems,06,280-291. doi: 10.4236/cs.2015.612028