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This paper presents research on a low power CMOS UWB LNA based on a cascoded common source and current-reused topology. A systematic approach for the design procedure from narrow band to UWB is developed and discussed in detail. The power reduction can be achieved by using body biased technique and current-reused topology. The optimum width of the major transistor device
M
_{1}
is determined by the power-constraint noise optimization with inner parasitic capacitance between the gate and source terminal. The derivation of the signal amplification S
_{21}
by high frequency small signal model is displayed in the paper. The optimum design of the complete circuit was studied in a step by step analysis. The measurements results show that the proposed circuit has superior S
_{11}
, gain, noise figure, and power consumption. From the measured results, S
_{11}
is lower than -12 dB, S
_{22}
is lower than -10 dB and forward gain S
_{21}
has an average value with 12 dB. The noise figure is from 4 to 5.7 dB within the whole band. The total power consumption of the proposed circuit including the output buffer is 4.6 mW with a supply voltage of 1 V. This work is implemented in a standard TSMC 0.18 μm CMOS process technology.

Ultra wide band (UWB) systems are a new wireless technology capable of transmitting data over a wide spectrum of frequency bands with very low power and high data rates. Among the possible applications, UWB tech- nology may be used for imaging systems, vehicular and ground-penetrating radars, and communication systems. In particular, it is envisioned that almost every cable at home or in an office will be replaced with a wireless connection that features hundreds of megabits of data per second [

One is the Direct-sequence UWB (DS-UWB) proposal. The DS-UWB proposal divides the whole band into two discontinuous bands with the lower band from 3.1 - 4.85 GHz and the upper band from 6.2 - 9.7 GHZ. The other is a proposal for a multiband orthogonal frequency-division multiplexing UWB (MB-OFDM UWB). The latter UWB proposal divides the whole band into 14 sub-bands 528 MHz that are grouped into five main bands [

The resistive feedback topology with a narrowband inductively degenerated common-source amplifier is an area-saving solution for good input matching in the 3 - 5 GHz UWB band [_{f} may be lowered to reduce additional noise. If the g_{m} of the transistor is raised, the Miller effect on R_{f} will also be increased. Therefore, a higher current dissipation and larger MOS area are required [

Some papers reporting on the common-gate amplifier have been suggested using wideband input matching as a solution by setting the input-transistor transconductance g_{m} equal to the reciprocal of the source resistance [

A common-source amplifier with a source degeneration inductor is one of the best approaches for narrowband application in terms of gain and noise performance [_{g}_{2} can reduce the noise figure in the cascode structure with current-reuse topology [

The proposed circuit of a common-source amplifier with low power UWB LNA has been demonstrated [

The proposed low power LNA is shown in _{1} and the buffer of the second stage. The first stage consists of the LC input matching network, body biased technique, and the cascode common source amplifiers M_{1} and M_{2} using the current-reused technique for low power design. The T-type LC filter is used for 50 Ω input matching and provides resonant frequency at 3 GHz for the high pass filter function. There are two transistors, M_{1} and M_{2} and both share the same drain current in a single path which saves power. The inductors L_{3} and L_{5} are used as the RF choke to avoid RF signal through the DC supply. A large value with L_{3} = 9 nH and L_{5} = 4 nH, respectively, is required. Inductor L_{4} is used as the peaking inductor. Capacitor C_{2} serves as the DC block capacitor and also builds up a RF signal path from transistor M_{1} to transistor M_{2}. Capacitor C_{3} serves as the bypass capacitor and

functions to make transistor M_{3} as the ground state at the source node. The value for C_{2} and C_{3} are assumed to be C_{2} = 2 pF and C_{3} = 6 pF, respectively [_{T} can be decreased by adjusting body voltage V_{B} to reduce the power consumption, and enhance the gain performance during the cascode stage. To improve the gain flatness, a couple inductor L_{6} is used. Finally, the source follower M_{3} and the current source M_{4} are used to as the output buffers. From the simulation, the measurements of our proposed circuit including the buffer are 4 mW and 4.6 mW, respectively.

We can develop a LNA design procedure of the common source with source inductor degeneration for narrowband application [

From the derivation of the power-constrained noise optimization, there are five steps necessary to complete the LNA design.

1) Determine the width of the optimum device M_{1} from the equation that follows:

where L is the length of transistor, R_{S} is the resistance of source stage, Q_{SP} is the quality factor of input stage and ω is the center frequency for which the design is made.

2) Bias the device with the amount of current allowed by the power constraint.

3) Select the value of source degenerating inductance to provide the desired input match.

4) Compute the expected noise from the following equation:

where γ is the thermal noise coefficient of transistor and α is the ratio of g_{m} (α = g_{m}/g_{d}_{0}), g_{d}_{0} is the transconductance at zero bias voltage.

5) Add sufficient inductance in the series with the gate to bring the input loop into resonance at the desired operating frequency.

From the former procedure, we can develop the optimum design for the UWB in a power constraint noise matching condition.

In the narrowband LNA circuit design, the optimum width of transistor M_{1} can be calculated by Equation (1) under power constraint noise optimization. In the UWB LNA circuit design, if the bias drain current I_{D} of the MOS device is initially set according to the power consumption requirement, then the noise can be estimated by Equation (2), and transistor M_{1} also can be determined. For NMOS devices, the drain current at the saturated region can be indicated [

where μ_{n} is the mobility of electrons, C_{ox}W is the total capacitance per unit length, L is the effective channel length and V_{GS} − V_{TH} is the overdrive voltage. From Equation (3), if channel length L and the overdrive voltage are kept at the constant, then the drain current is proportional to the capacitance. Since a MOSFET operating in saturation produces a current in response to its gate-source overdrive voltage, the transconductance gm can be expressed as the following:

From Equation (6), g_{m} represents the transconductance of the device, for a high g_{m}, a small change in V_{GS} results in a large change in I_{D}. And it can be seen that g_{m} decreases with the overdrive if I_{D} is constant. The above descriptions from Equation (1) to Equation (6), the size of transistor M_{1} is located at some range in the low noise figure from the power constraint. This phenomenon has been reporeted in the following papers [_{1} during the first stage which is an important factor to control the total noise figure of the circuit. Here, we adopted the power constraint noise optimization that accompanies with parasitic C_{gs} of transistor M_{1} to deal with the dimension of the size. In the circuit design, the multi fingers for layout profile are used for transistor to reduce the gate resistance (R_{g}) and noise figure for good behavior.

It is known that the parasitic capacitance is varied by the device size in the high frequency region. If gate resistance R_{g} is considered and _{in} can be obtained as the following Equation (7):

where s is equal to j2πf. As described above, if the budget of power consumption is determined, then the noise figure and the range of the M_{1} device size are also obtained as shown in

Based on the power constraint noise matching, the noise figure is raised with drain current being decreased as shown in _{1} is viewed as a part of the input for the impedance matching network, then the transistor size can be optimized for input matching in the whole band. _{11} of the input impedance matching with different transistor sizes. If

the width of the device is 100 µm, the locus of S_{11} must be improved in the low band. On the contrary, if the width of the device is larger than 160 µm, then the locus of S_{11} must be improved in the high band. Therefore, the better transistor width is close to 130 µm as shown in

In the single band or narrow band low noise amplifier, the S_{11} of a common source with inductive degeneration is better than without inductive degeneration. This principle is also fitted to ultra wideband LNA.

The input impedance of the common source inductor L_{s} included in the circuit can be modified from Equation (7) as follows:

Here g_{m}_{1} is the transconductance of transistor M_{1}, then, owing to the contribution of L_{2}, the locus of S_{11} is different from the one in which we omitted L_{s} in the circuit for input matching. This phenomenon can be seen in _{s}, they both have good S_{11} lower than −10 dB in the whole band. Of course,

we must check the effects of gain and the noise figures.

From

Finally, whether the source inductor is adopted or not in the circuit for wideband application, there is a little difference of performance from the effect of gain or noise figure. So the source inductor is omitted to save the chip size in our proposed circuit. The detail usage of source inductor is more described in the references [

Cascode topology is commonly used to save power and for high gains with a fixed supply voltage application. Recently, the current reused structure has been popularly adopted [_{1}, C_{2}, L_{1}, L_{2}, M_{1}) is designed to resonate at the lower band, and the second stage (R_{1}, L_{4}, L_{5}, M_{2}) is designed to resonate at the higher band.

For RF signal analysis, the forward gain A_{v} from signal source V_{sig} to output voltage V_{out} can be expressed as the following Equation (9):

where A_{V}_{1} is the gain of transistor M_{1}, A_{V}_{2} is the gain of transistor M_{2} and A_{V}_{3} is the gain of transistor M_{3}, respectively. The detailed derivation can be seen in the appendix.

The output resistance R_{out} is approximated with a low frequency model as in Equation (10):

When g_{m}_{3} is the transconductance of transistor M_{3}, r_{o}_{3} and r_{o}_{4} are the output resistance of transistors M_{3} and M_{4}, respectively. For UWB application, the inter stage inductor L_{6} can resonate with the parasitic capacitor (C_{gs}_{3}) of transistor M_{3} which creates gain peaking at the high frequency band at about 11 GHz. Of course, it also provides the best gain flatness of the proposed circuit. For achieving good gain flatness, the optimization value of L_{6} and L_{4} are 2.93 nH and 0.48 nH, respectively.

The body biased technique is not used for designing in traditional electronic circuitry with respect to body effect. Recently, self forward body bias and adaptive body bias have been adopted to design circuits that use less power in narrow band considerations [

Since the standard CMOS process is without a multiple gate oxide option, the threshold voltage V_{T} can be calculated by adjusting with V_{SB} as shown in Equation (11):

where V_{SB} is the source to body voltage, V_{T}_{0} is the threshold voltage for V_{SB} = 0, γ is a process dependent parameter, and

There are two models to understand the body bias technique with analytical expression of the circuit.

1) Body effect analog modeling

First, assuming

This Equation (12) highlights a linear relationship between the threshold voltage of the MOS transistor and the potential applied to its bulk.

2) DC mode

The MOS drain current is given by:

For a given V_{GS}, I_{D} current flowing through the MOS transistor depends on bulk-to-source voltage. Hence, transistor biasing can be controlled thanks to the body effect in a DC approach. However, one has to pay attention to the fact that the V_{SB} range is limited. Indeed, if the V_{T} enhancement induces no significant parasitic constraint on DC characteristics despite the current decrease, the reduction of the threshold voltage can disturb the transistor effect.

Assuming that V_{SB} is lower than roughly speaking 0.7 V, the bulk-to-source PN junction of the NMOS transistor is thus forward biased, producing a leakage current and aborting the transistor functionality. It sets up the limit whose body effect is useful to implement a function thanks to the DC approach. To use body bias NMOSFET, a deep Nwell process is needed. In addition, a deep Nwell process can reduce noise cross-talk through the substrate [

This circuit design with body bias technique allows for a reduction in power consumption. A 0.45 V body bias is used to make the transistors in the strong inversion region. It can be seen from

The gain and NF of the LNA are drawn versus V_{BS} as shown in _{BB} = 0.45 V. Practically, the forward body voltage is limited to 0.4 - 0.7 V.

To further investigate the influence of the bias conditions on the noise figure (NF), the simulated values versus gate to source voltage (V_{GS}) for the different body bias voltages are demonstrated in _{GS} and V_{BS} are as low as good for low power design. Therefore, the voltage V_{G} is chosen as 0.55 V.

However, how much power can be reduced by the body biased technique is still uncertain. In the circuit, if the parameter gain and S_{11} are in the same condition, then without body bias, the simulation of power consumption in the core circuit is 4.44 mW for 1.2-V supply voltage and 7.23 mW including the output buffer. With body bias, the simulation of power consumption in the core circuit is 3.24 mW and 4.1 mW including the output buffer. The measurement of the power consumption is 3.32 mW and 4.6 mW including the output buffer.

^{2}. In _{11}) is lower than −12 dB, but in _{22}) is lower than −14 dB from 3.1 GHz to 10.6 GHz, respectively. The power gain, whose peak value is 13 dB, is shown in _{3}) is −14 dBm. The total power consumption is 4.6 mW at 1 V supply voltage.

To compare the overall performance of our LNAS with previously published ones, a figure of merit (FOM) that takes into account the gain, NF, BW, IIP_{3}, and the DC power consumption of the LNA is defined as [

Where BW is the bandwidth, P_{D} is the power consumption in milliwatts, the values of gain and noise factor F are their absolute values, IIP_{3} is indicated as linearity of the amplifier or circuit, and also called the input third-order intercept point.

The comparison of the proposed work with other reported papers are shown in

Reference | [ | [ | [ | [ | [ | This work |
---|---|---|---|---|---|---|

Technology (CMOS) | 0.18-μm | 0.18-μm | 0.18-μm | 0.18-μm | 0.18-μm (LNA2) | 0.18-μm |

Frequency (GHz) | 1 - 10 | 3.1 - 10.6 | 1.2 - 11.9 | 3.1 - 10.6 | 3.1 - 10.6 | 3.1 - 10.6 |

S_{11} (dB) | <−8 | <−11 | N/A | <−13.5 | <−8.6 | <−12 |

S_{22} (dB) | <−10.8 | N/A | N/A | <−10.1 | <−10 | <−14 |

S_{21MAX} (dB) | 10.5 | 11/14 | 10.6 | 12 | 12.26 | 13 |

NF_{min} (dB) | 4.2 | 5.1/4.5 | 3.4 | 5.27 | 3.84 | 4 |

IIP_{3} (dBm) | 1 | −12 | −6.2 | −2.23 | −11 | −14 |

P_{DC_CORE} (mW) | 12.65 | 9/21 | 20 | 4.5 | 10.34 | 3.32 |

Area (mm^{2}) | 0.69 | 0.46 | 0.59 | 1.03 | 0.536 | 0.928 |

FOM (only core LNA) | 4.58 | 4.09/6.41 | 4.77 | 8.44 | 6.26 | 12.01 |

FOM__{IIP3} (only core LNA) | 5.77 | 0.258/0.403 | 1.14 | 5.05 | 0.495 | 0.773 |

performance of gain and low power dissipation.

In general case of low noise amplifier, most of the circuit design did not consider the linearity characterization. The linearity has a serious effect on the power amplifier. Therefore, we can show that our performance of FOM is better than others, and FOM_{_IIP3} is fairly good but still not the optimal choice.

In this paper, a UWB low noise amplifier with body bias technique has been presented. The proposed body bias technique is employed to achieve low power consumption. The T-type matching network used for input matching to achieve gain flatness and frequency bandwidth. The power consumption is as low as 4.6 mW with a 1 V supply voltage. From 3.1 to 10.6 GHz, the maximum power gain is 13 dB and the minimum noise figure is 4 dB.

This project was supported by the National Science Council, (NSC100-221-E-224-072), Taiwan , ROC. The authors wish to thank the Chip Implementation Center (CIC) and TSMC for supporting the CMOS process and further fabrication.

Meng-TingHsu,Kun-LongWu,Wen-ChenChiu, (2015) Systematic Approaches of UWB Low-Power CMOS LNA with Body Biased Technique. Wireless Engineering and Technology,06,61-77. doi: 10.4236/wet.2015.63007

This section is the calculation of gain.

where V_{out} is the output voltage, V_{Sig} is the signal source voltage, A_{v}_{1} is the gain of transistor M_{1}, A_{v}_{2} is the gain of transistor M_{2} and A_{v}_{3} is the gain of transistor M_{3}.

The gain of the transistor can be expressed by Equations (2)-(4):

where V_{d}_{1} is the voltage of transistor M_{1} drain terminal, V_{gs}_{1} is the voltage on C_{gs}_{1}, V_{g}_{1} is the voltage of transistor M_{1} gate terminal.

where V_{L} is the output voltage of transistor M_{2}, V_{d}_{2} is the voltage of M_{2} drain terminal, V_{gs}_{2} is the voltage on C_{gs}_{2}.

where V_{s}_{3} is the voltage of transistor M_{3} source terminal, V_{g}_{3} is the voltage of M_{3} gate terminal.

We can calculate each ratio of the previous description from Equations (2) to (4) by the backward direction. Therefore, we can obtain the following equation from (5) to (12).

In the circuit, analysis of the high frequency models always meets the Miller’s theorem. The ratio of drain to

gate node with transistor M_{1} is by _{2} is also simply expressed as

K_{1} and K_{2} can be obtained in equations (13) and (14), respectively. Finally, we can get the total overall gain of the complete circuit in Equation (1).