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This paper describes the gate electrode resistance of MOSFET and non-quasi-static (NQS) effect for RF operation. The vertical current paths between the silicide layer and poly-silicon are considered in the gate electrode. The vertical current paths are not effective in long-channel devices, but become more significant in short-channel devices. The gate resistance including vertical current paths can reproduce the practical RF characteristics well. By careful separation of the above gate electrode resistance and the NQS effect, the small-signal gate-source admittance can be analyzed with 130-nm CMOS process. Elmore constant ( κ) of the NQS gate-source resistance is about five for long-channel devices, while it decreases down to about three for short-channel devices.

CMOS device technology realizing low-power, large-scale integration and low-cost to manufacture is recently matching demands for miniaturization, low-power operation in wireless communication systems [_{t}, against bipolar junction transistors and compound semiconductor devices, which are popular in RF circuits [

One of the important issues of the MOSFET model in RF operation is related to effective gate resistance which influences input impedance, maximum oscillation frequency f_{max}, and noise performance [_{gs}, which causes a relaxation-time dependent phenomenon of channel charge response for a time-varying input signal, so called non-quasi-static (NQS) effect [_{gsi} of the MOSFET operating in saturation region is approximately given by

where g_{m} is the transconductance, and the Elmore constant κ is five for long-channel and is reported to be as small as one for short-channel devices [

In this paper, we present high-accuracy gate electrode resistance model. The model presented includes the vertical current paths between the silicide and poly-silicon layers in MOSFET. By careful separation of the gate electrode resistance and the NQS effect, the small signal gate-source admittance can be analyzed. From these values, the κ is derived.

This paper is organized as follows. Section 2 describes gate electrode resistances with vertical current paths. Section 3 presents a MOS equivalent circuit which includes extrinsic and intrinsic parameters, and mentions method of parameter extraction. In Section 4, some parameters extracted in 130-nm CMOS process as well as κ are verified and discussed. Finally, conclusions are drawn in Section 5.

The gate of conventional MOSFET model is composed of gate insulator, poly-silicon, silicide and metal.

and vertical resistance of the poly-silicon itself [^{2} (TiSi_{2}) [^{2} (NiSi) [

Each parts of gate electrode resistance can be expressed with lumped elements for the signal path length in a horizontal gate width direction dz using a transmission line model as illustrated in _{cg} is unit gate contact resistance between the silicide and poly- silicon, ρ_{sili} is the sheet resistivity of the silicide, ρ_{int} is an interface resistivity between the silicide layer and poly-silicon, ρ_{vp} is the vertical resistivity of poly-silicon layer per unit dimension. C_{ox} is unit capacitance of the gate insulator. For simplification in mathematical expression, _{gc} is defined as the capacitance between the gate and channel, we can consider it as

Considering the steady state at the angular frequency ω in _{vp}, is given by

From the manipulation described in Appendix, the gate electrode resistance seen from the gate contact position for unit gate finger with length W_{f} is expressed as

where k is 1 and 1/4 for a single-side and a both-side gate connections, respectively.

Additionally, considering the gate contact between the silicide and metal as well as the gate extension to the channel area in a similar way based on the previous work [_{f} is expressed as

where W_{ext} is the distance between the channel area edge and gate contact, and N_{cg} is the number of gate contacts per finger [_{f}W_{f}, which originates from the vertical resistance elements. As the channel area decreases, this influence increases.

In low-frequency operation, carriers in the channel can respond immediately to the applied terminal voltages, which correspond to charging and discharging of the gate-source capacitance C_{gs}. This is considered as quasi- static operation. On the other hand, as the operation frequency gets much higher, the channel resistance influences response time of the carriers, which is NQS operation. Although the transconductance, drain conductance and large-signal operation are influenced by the NQS effect, the influence of the small-signal gate-source admittance y_{gs} is crucial in the multi-band and wide-band LNA designs. This paper focuses on the small-signal gate-source admittance.

To estimate the NQS effect, the careful parameter extraction for MOSFET model is required. _{gsi} and R_{gdi} in _{ge} is a gate electrode resistance, R_{de} and R_{se} are series resistances of drain and source, and C_{gse} and C_{dse} are overlap capacitances between gate/source and drain/source. Extraction method separates extrinsic and intrinsic parameters from two-port parameters of the MOSFET. In the first step, the external resistances (R_{ge}, R_{de} and R_{se}) and the external capacitances (C_{gde}, C_{gse} and C_{dse}) are de-embedded from the two-port parameters of the MOSFET, using the

de-embedding technique [

To estimate the external parameters, the cold biasing (V_{GS} = V_{DS} = 0 V) is utilized. It is assumed that the intrinsic parameters except for drain-source conductance g_{ds} are not presented in cold bias. External parameters are nearly independent on V_{GS}. Thus, the Z-parameters of the MOSFET in the cold biasing can be obtained as follows:

In the cold bias condition, g_{ds} is negligibly small. Assuming it, real parts of the Z-parameters in high frequency can be approximated as

From these equations, R_{ge}, R_{de} and R_{se} can be estimated. In addition, Using Equations (5)-(10) with the same assumption of small g_{ds}, imaginary parts of the Z-parameters can be approximated as.

From these equations, C_{gse}, C_{gde} and C_{dse} can be estimated.

The intrinsic Y-parameter matrix

Based on the equivalent circuit shown in

In this work, instead of on-chip high-frequency S-parameter measurement, simulated small-signal S-parameters are used with a RF MOSFET model (BSIM4 with GATEMOD = 3 [

The external gate resistance R_{ge} is extracted by using Equations (5)-(10), and is compared with calculated ones by using Equation (4). The results are illustrated in _{ge} with and without the second term (solid and dotted lines in ^{2} which is reasonable value considering the reported typical values [

Based on the extracted external parameters, NQS gate-source resistance R_{gsi} and transconductance g_{m} are extracted by using Equations (19) and (21). In this parameter extraction, to neglect high-order NQS effect [_{gsi} on drain-source voltage V_{DS} at the gate-source overdrive voltages _{gsi} has little V_{DS} dependence.

_{gsi} and g_{m} with Equation (1) as a function of gate length. As mentioned above, κ is around 5 for L > 1 μm. For L < 1 μm, it decreases to about 3, which may originate from velocity saturation [

is smaller than in the non-velocity-saturation source-side region. However, the value of κ around one, as reported in previous works [

In this work, the gate electrode resistance of MOSFET and NQS effect are analyzed using 130-nm CMOS process. The vertical current paths between silicide layer and poly-silicon are considered in MOSFET. The vertical current paths are not effective in the devices with large channel area, but become more significant as the channel area decreases. The gate electrode resistance including vertical current paths can reproduce well the practical RF characteristics. With the scaling of CMOS technology, this effect is not considered till now in RF CMOS circuit designs, but it has a significant effect in the design of multi-band and wide-band CMOS LNAs. By careful separation of the above gate electrode resistance and the NQS effect, the intrinsic small-signal parameters were extracted. The high-accuracy analysis considering physical characteristic with the vertical elements is verified. Elmore constant of the NQS gate-source resistance (κ) about five was confirmed for the long-channel devices, while it decreases down to about three for the short-channel devices. The value of κ around one, reported in previous works, could not be confirmed even for minimum gate length in this work. The NQS effect in short-channel devices may have significant and complicated dependence on device structure. For further studies, the analyses on various processes with various device structures are more required for RF CMOS circuit designs.

This study is supported by the VLSI Design and Education Center (VDEC), University of Tokyo, in collaboration with Agilent Technologies Japan, Ltd., and Cadence Design Systems, Inc.

The lumped elements of MOSFET's horizontal and vertical gate resistance can be composed as like

Thus, the voltage

where

The boundary conditions to obtain V_{+} and V_{−} in case of a single-side gate connection (

where k is 1 and 1/4 for a single-side and a both-side gate connections, respectively. The approximation is valid

for