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Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). Many power reduction techniques have also been proposed from the system level down to the circuit level. High-speed computation has thus become the expected norm from the average user, instead of being the province of the few with access to a powerful mainframe. Power must be added to the portable unit, even when power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Techniques for low-power operation are shown in this paper, which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. The threshold vol-tages of the MTCMOS devices for both low and high V
_{th} are constructed as the low threshold V
_{th} is approximately 150 - 200 mv whereas the high threshold V
_{th} is managed by varying the thickness of the oxide T
_{ox}. Hence we are using different threshold voltages with minimum voltages and hence considered this project as ultra-low power designing.

Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level [

A) Supply Voltage Scaling

To reduce the power consumption, the scaling power supply voltage is most effective method [_{dd} for a 4-bit carry look-ahead adder in 0.18 μm process technology [

However, the supply reducing voltage also the delay is increases. The relationship between V_{dd} and the delay, T_{d}, can be expressed as

From the Equation (1), when V_{dd} approaches the threshold voltage, V_{t}, the delay increases drastically [

B) Reducing Effective Capacitance

When the performance loss in throughput due to lowering the supply voltage is not acceptable. The low power consumption in CMOS circuits can also effective the reducing capacitance. The effective capacitance is defined by the product of the physical capacitance and the switching activity [

where α_{0}_{-}_{1} is the node transition activity factor and C_{L} is the load capacitance which refers to physical capacitance. The switching power consumption can be rewritten as

From the above equation, reducing the switching power consumption can be achieved by minimizing both of the physical capacitance and the switching activity [

Physical Capacitance Reduction:

The physical capacitance can be reduced through selecting the appropriate circuit style and optimizing the transistor sizes.

The different circuit and logic styles result in different gate and diffusion capacitance of the transistors in a combinational logic circuit [

As shown in

The capacitive load that originates from transistor capacitance and interconnect wiring can be reduced by optimizing transistor sizes whenever possible and reasonable. In general, increasing the transistor sizes results in a large (dis)charging current and simultaneously increases the parasitic capacitance. On the other hand, reducing the transistor sizes will result in decreasing input capacitance that may be the load capacitance for other gates and lowering the speed of the circuit. Thus, the objective of transistor sizing is to obtain the minimum power dissipation under given performance requirements. In order to explain how to make transistor sizing, let us consider a static inverter driving a load capacitance being composed of an intrinsic (diffusion) and an extrinsic (wiring and fan out) capacitances. When the total load capacitance to the gate output is dominated by the diffusion capacitance, the smallest possible sizes of the transistors should be used for obtaining the lowest power consumption. Otherwise, if the load capacitance is dominated by the extrinsic component [

C) Switching Activity Reduction

The dynamic power consumption of a circuit is strongly related to the switching activity of the circuit [

Glitches, or dynamic hazards, are unwanted signal transitions which occur before the signal settles to its intended value. Glitches can be generated and propagated in both data path and control parts of the circuits. The simulation result from the circuit simulator (Specter) was obtained under the different conditions. The spurious transitions consume extra power compared to the glitch-free scenarios. The number of spurious transitions in a circuit depends on the logic depth, input patterns, and intermediate carry signal states etc.

The glitching activity in static circuit designs can be minimized by selecting structures with balanced signal paths and reduced logic depth. The tree structures can be applied to implement a circuit with both of the balanced signal paths and less logic depth, while the chain structures are quite the contrary. A good example in

Another possible approach to eliminate the spurious transitions is to use dynamic logic circuits instead of static logic, since any node in dynamic logic circuits can only undergo at most one transition per clock cycle.

D) Reduction Technique for Leakage Power

The number of typical reduction for leakage techniques fall in two categories, either leveraging the stack effect or increasing the transistor threshold voltage. Forcing transistors into stacks is not a scalable solution and its implementation becomes very complicated for large designs. There are three main reasons for minimizing leakage current. They are (i) source/drain junction leakage current which is due the junction acts as an diode in reverse bias when the transistor is in sleep mode. i.e. in OFF. (ii) Is gate tunneling leakage current which flows through the oxide to substrate? If the gate oxide is thin, then the current increases exponentially. And the third one is (iii) sub threshold leakage current, which is a current from source to drain. It is diffusion current built by minority carriers in the channel in the MOS devices [

As technology scales into the deep-submicron (DSM) regime, standby sub threshold leakage power increases exponentially with the reduction of the supply voltage vdd and the threshold voltage vth. For many event driven applications, such as mobile devices where circuits spend most of their time in an idle state with no computation, stand by leakage power is especially detrimental on overall power dissipation [

Another use of the leakage feedback gate is to modify the static MTCMOS flip flop to eliminate the need for the parallel inverter to re circulate data. The leakage feedback structure can be used instead, which does not slow down the critical path because no extra capacitances are introduced on internal nodes [

Simulations were performed on the various MTCMOS flip flop architectures in a 0.16 u technology with high Vt approximately 0.15 V and low V_{t} approximately 0.05 V (defined the 10 nA @ 10 um point).

In this paper, several existing power reduction techniques are discussed and a novel circuit design technique to minimize sleep mode power consumption due to leakage power in CMOS technology is discussed. This circuit technique provides significant energy savings in sleep mode without any speed degradation or die area overhead. Moreover, it is almost independent of technology scaling and has no circuit design complexity. This paper presented several dual-threshold voltage circuit techniques that can help reduce sub threshold leakage currents during standby modes for combinational logic blocks [

technique which enables to further reduce the total leakage w.r.t. the case of high-sleep transistors [