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A major concern in modern smart-phones and hand-held devices is a way of mitigating the time interval error (TIE) perceived at high-speed digital transits along the traces of the circuit-board (rigid and or flexible) used in baseband infrastructures. Indicated here is a way of adopting a planar fractal inductor configuration to improvise the necessary time-delay in the transits of digital signal phase jitter and reduce the TIE. This paper addresses systematic design considerations on fractal inductor geometry commensurate with practical aspects of its implementation as delaylines in the high-speed digital transports at the baseband operations of smart-phone infrastructures. Experimental results obtained from a test module are presented to illustrate the efficacy of the design and acceptable delay performance of the test structure commensurate with the digital transports of interest.

In the context of the state-of-the-art smart-phones and other mobile/hand-held devices, the data bit-rates adopted at baseband levels could be significantly high (~500 Mbps); and, such streams of high-speed bits are often transferred between chips and/or various circuit nodes during baseband signal-processing, for example, between an image-sensor and an image sensor processor (ISP). To negotiate such transfers, numerous copper-traces are envisaged at the board-level formed either on a single surface or in multiple board/flex stacks. Normally, such trace-lines are of different lengths so as to accommodate ad hoc interconnections and digital transits between the pins across any two devices placed at distinct locations on the board. Further, several of these lines may run almost parallel to each other with jagged tracks. An example of such a track is illustrated in

As a result of varying physical lengths of the traces, the digital bits transported from one end on any given trace will arrive at the pin of signal destination (terminated on the chips in question) with a specific extent of transmission-line dependent delay. However, this delay could be distinctly variable in each of the traces due to varying path-lengths involved and varying bit-rates of information transmitted. That is, the observed delay is specific to each line-length as defined by the associated line-parameters namely, the inductance and the capacitance per unit length and the digital signature of the information communicated. The resulting data dependent jitter (DDJ) [

Hence, the data pulses received with varying delays traversing different parallel lines may become unusable for applications and digital-processing efforts at the receiving devices due to the associated randomness of delay variations tied to the TIE. Therefore in practice, delay-lines are introduced in each trace to compensate for the transit-delay so that the digital data supported are displaced in time on ad hoc basis and get synchronized at the receiving end as needed minimizing the influence of TIE.

Traditionally, at circuit-board level, physical inductors in solenoidal forms are designed, trimmed and incorporated on transmission-lines so as to offer a desired inductance (especially at RF sections) [

Yet, considering the specific needs of modern smart-phones or similar handheld gizmos vis-à-vis emulating tailor-made extents of delays compatible for high-density traces (at baseband levels), a novel design is proposed in this paper toward synthesizing a new class of planar inductors using fractal geometry. Shown in

It is surmised in this study that the fractal planar inductors can be designed to facilitate a desired delay-time in a constrained on-board area. Apart from spiral, other options such as meander line, Hilbert structure, Minkowski curve, Koch’s curve etc. can be adopted in making fractal geometry. Conceived thereof in vogue, are structures to optimize the delay-line performance versus space-filling considerations as warranted in baseband, high-speed operations of smart-phones and/or similar devices. Associated higher order fractal curves enable design options with good space-filling properties. Most of such fractal structures have been conceived in the contexts of antenna designs and related RF units as reported in [

This paper is organized to describe a test study on a proto-type of fractal inductor geometry illustrated in

The physically transmitted baseband signal represents a “digital-over-digital” transmission of pulse trains. In modern context of 3G through 4G considerations and associated LTE implications, the baseband data handled in the infrastructures of smart-phones (and similar devices) is used at specific versions of processors with chip-designs and system-on-chips (SoCs) that accommodate generous audio, and video digital signal processing. Such processors are required to meet multi-standard integration, reduced power dissipation and facilitate extra key functions for next-generation smart, handheld devices. Relevantly, baseband processors provide efficient operations with cost-effective multimedia application-specific processing for entry-level 3G as well as next-generation/evolving 4G systems. Further, in such complex baseband chip-specific operations, the underlying applications invariably dictate the use of high-speed bit rates.

For example, considering video-processing support for 10/12 Mpixels imaging and 720 p video-playback plus accelerated 2D/3D graphics, operational needs push the processor speeds up to 1GHz or even higher. Concurrently, related transmissions point out the gravity of multiple high-speed transports on the limited-space circuitboard (and/or flexible-board) layouts. Together with the packaging designs of the components and chips on the board, the interconnections that support the said digital transports are crowded and routed haphazardly. Hence, the transmission-lines (traces) envisaged thereof are high in density (per unit area) and of varying lengths. Therefore, the digital transports end up in TIE-related issues that call for effective mitigations.

Commensurate with the types of digital processors and interconnections mandated at the baseband infrastructure, the circuit-board and/or flex-boards have to be carefully designed in practice and traces should be laid out with minimized lengths and routing to avoid not only the TIE, but also crosstalk effects. Specifically, the items of planar structure needed for TIE mitigation via inductor emulations as delay-lines are described below with relevant basics.

Planar Inductors: An OverviewVariety lies in conceiving delay-line topologies and basically, planar delay-lines are made using meander-lines or spiral-line configurations. Functionally, a delay-line offers a desired extent of time-delay between circuit components. In digital domain such delay requisites have been achieved classically with phase-shifting electronic switches [

However, such serpentine delay structures may introduce spurious dispersions that signal appear along with the signal as if, it is arriving earlier than would be expected, as decided by the total electrical length of the line. This is typical with the disposition of two or more adjacent lines closely spaced; further, such proximal layout would lead to electromagnetic (EM) coupling as well and related crosstalk effects [

Traditionally, as mentioned earlier, fractal structures on printed circuit-boards have been advocated in practice toward emulating fractal antennas, fractal capacitors and fractal inductors [

Higher order fractal curves are characterized with good space-filling properties and tend to show better efficiency than standard inductance structures having the same overall dimensions. As such, fractal-based RF structures have emerged successfully in making of capacitors, antennas and related resonating components. Fractals are a class of non-Euclidean geometries with unique attributes. A fractal design conforms to a self-similar geometry that maximizes the length or increases the parameter of a unit in emulating a desired EM characteristic within a given total surface area or volume. Fractal structures, in general, are referred to as multilevel and space-filing curves with the repetition of a motif over two or more scale sizes. With the iteration of the motif thereof, fractal structures are compactly formed. For example, as proposed in the present study, a fractal inductance can be formed as a space-filling curve in the shape of a shrunken fractal helix (

Basically planar components like capacitors and inductors can be fabricated as printed elements with small tolerances using the modern artwork of photolithographic process relevant to printed-circuit boards [

The test inductor for the intended delay-line application is fabricated as a single-layer copper trace structure on the top of a standard printed circuit-board using conventional photolithographic process. As illustrated earlier in

Measurement studies on the test fractal inductor are performed to estimate the time-delay on a signal at a given frequency that can be achieved by considering two or more spirals at a time. Relevant circuit used for testing is shown in

Planar geometry

output waveforms of the test circuit. Typical scope-plots are shown in

The time-delay (d) is obtained from the measured phase shift (f) across the series-connected L-structures used in the test. It is presented in normalized values with respect to the signal period (T) in

spirals (L_{10} and L_{11}) of the fractal geometry. It can be consistently observed in

Based on the novel concept structure and achievable delay demonstrated in the prototype model studied, more work can be exercised as regard to other fractal structures such as square-loop version, Koch fractal geometry, Hilbert fractal curve etc. Fabrication issues like ground-plane/ground counterpoise effects and circuit-board layer considerations need more careful studies. The proposed strategy may however, pose fabrication and/or manufacture difficulties at present. But, the technology details as in [