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In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. In the present paper, we show a design of the reversible comparator based on the quantum gates implementation of the reversible DG gate. The reversible DG gate is designed by using 3 × 3 quantum gates such as NOT, CNOT, Controlled-V and Controlled-V^{+} gates. Also, we have used the TR gate and various types of quantum gates in the implementation results. Low power three-bit comparator is designed using DG Gate, New Gate and Fredkin Gate. In order to evaluate the benefit of using the DG gate proposed in this paper, one-bit comparator is constructed. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.

Conventional combinational logic circuits dissipate heat for every bit of information that is lost during their operation [

Bennett [

There are two Boolean constants, 0 and 1. Reversible circuits are those circuits that do not lose information.

These circuits can produce single output vector from each input vector, and conversely, there was a one-to-one mapping between output and input vectors. Hence, an N × N reversible gate can be represented as:

where Iv and Ov can be shown the input and output vectors respectively; the significant cost metrics in the synthesis of reversible logic circuits are the number of garbage outputs, delay and quantum cost [5,6]. Any unitary operation must be reversible. Thus, quantum networks effecting primary arithmetic operations such as addition, multiplication and exponentiation cannot be directly infered from their classical Boolean counterparts (classical logic gates such as AND or OR or EXOR are irreversible). Therefore, Quantum Arithmetic must be made from reversible logic combinations [

In this paper, we present various designs of a three-bit comparator circuit using existing reversible logic gates. The present paper proposed a new gate, called reversible DG gate which was used in the design of comparator. All the comparators have been modeled and investigated using VHDL and Quartus II.

The detailed cost of a reversible gate associates with any specific realization of quantum logic. A short description of the gates are given below.

A. The NOT Gate A NOT gate is a 1 × 1 gate performed as shown in

B. The Controlled-V and Controlled-V^{+} Gates The Quantum cost of a Reversible gate is computed by counting the number of V, V^{+} and CNOT gates [^{+} gates are shown in Figures 1(b) and (c).

The Controlled-V and Controlled-V^{+} quantum gates have some properties that are shown below:

These equations depict that two V or V^{+} gates in series are equivalent to a NOT gate; and two V and V^{+} in series, are equivalent a BUFFER gate.

C. Feynman Gate The most popular (2, 2) one-through reversible gate is the Feynman gate [

The input double (A, B) depends on its output double (P, Q) as follows.

If A = 0 then Q would be equal to B. If A = 1 then showed the complement of the input (B).

Hence, it is called as quantum XOR and also called as CNOT (1-NOT).

D. Fredkin gate Fredkin gate [

Figures 4(a) and (b) offer the performance of the Fredkin gate as AND and OR functions respectively.

E. New gate The New gate [

The New gate is one of the most popular reversible as represented in

F. BVF gate This is a (4, 4) reversible logic gate [

G. TR gate Recently Thapliyal and Ranganathan in [^{+} gates, 2 V gate and 1 CNOT gate in its structure.

TR gate and Quantum implementation of TR gate have represented in Figures 7(a) and (b) respectively.

This paper presents a new (3, 3) reversible gate, “DG”,

with inputs (A, B, C) and outputs P = A, Q = (A ⊕ B)', R = AB' ⊕ C that is shown in

The two numbers are equal if all pairs of significant digits are equal; meaning A3 = B3 and A2 = B2 and A1 = B1.

To check for this equality, we use the XNOR gate as we did previously.

So we have seen three bit comparator (A = B) using classical gates as shown in

In the same way, the following classical gate A > B can be considered for a three bit comparator which is shown in

If we want to have the output A = B, DG and BVF Gates can be used. The results are shown in

Two DG Gates can be put instead of BVF Gate to reduce the number of gates. The results are shown in

Reversible three bit comparator is implemented with various types of reversible logic gates as shown in Figures 13 and 14 respectively.

The proposed circuit of the three bit comparator is evaluated in terms of number of reversible gates used and garbage outputs generated. Tables 4 and 5 show the evaluation of the proposed circuits.

The results show that DG gate reduces the number of gates and garbage outputs.

In the proposed one-bit comparator design, we have investigated FA > B and FA = B and the third condition FA < B is produced from the first two outputs. Therefore the design recitation leads to

The results are shown in

rently. Tables 6 and 7 show the evaluation of the proposed circuits.

In the mentioned paper one bit comparator has better function in comparison with Nagamani et al.

A good synthesis for reversible logic should not create an excessive “garbage” or “waste of outputs”. Hence, the components are chosen so that the designed scheme has the desired characteristics. One bit comparator can be represented by 2 DG gates and 1 FG gate, as shown in

Two same outputs of this

Reversible logic gates are extensively known to be compatible with future computing technologies which approximately dissipate zero heat [

Conventional computers generate heat and waste much energy. In order to make a computer faster and lower power, consumption proposed reversible logic gates. In this paper, we have presented new designs of reversible one and three-bit comparators based on the quantum gates implementation of the reversible TR and DG. The main goal of this paper is optimized in terms of number of garbage outputs, gate count and quantum cost for comparator designs. The proposed DG gate can be combined with TR gate and various types of reversible logic gates to design minimal quantum cost and garbage less reversible circuits.

The newly proposed DG gate can be used for imple-

menting concurrent EXOR and EXNOR output functions. Hence, three outputs of DG gate have efficient results for comparator designs. In this paper, one-bit comparator has better performance comparatively.