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This paper is devoted to temperature analysis on power RF LDMOS with different feature parameters of die thickness, pitch S length and finger width. The significance of these three parameters is determined from temperature comparison obtained by 3D Silvaco-Atlas device simulator. The first three simulations focus on temperature variation with the three factors at different output power density respectively. The results indicate that both the thinner die thickness and the broaden pitch S length have distinct advantages over the shorter finger width. The device, at the same time, exhibits higher temperature at a larger output power density. Simulations are further carried out on structure with combination of different pitch s length and die thickness at a large 1W/mm output power density and the temperature reduction reaches as high as 55%.

RF LDMOS has become the most popular RF power technology for base station applications. However, as demand for much higher power level, device temperature increases due to self-heating effects taking place inside the active area. Thus, the electrical characteristics such as reliability and linearity are strongly affected [1,2]. As a result, treatment for thermal effect are mainly from circuit view with compensation network such as adaptive bias [

A typical structure is illustrated in

A half-structure is used to study the temperature distribution for the device symmetry. The feature parameters are as follows: finger width = 400 μm, die thickness = 60 μm, pitch s length = 25 μm and LDD length = 2.5 μm.

Boundary conditions definition is important in thermal simulation [

The junction temperature description with electrothermal model is shown as [

The instantaneous dissipated power determines the instantaneous rate of heat that is applied to the transistor. Thermal resistance describes the steady state temperature

and thermal capacitance expresses the dynamic behavior. The dynamic behavior only needs to be accounted for small tone spacing. The steady character related to the thermal resistance is determined by the device structure.

3D thermal distribution simulation is implemented in Silvaco-Atlas. The steady-state lattice heat diffusion is given as:

where T represents the steady-state temperature, k represents the thermal conductivity and q represents the power generation per unit volume in the heat source.

The thermal conductivity is generally temperature dependent and can be described by:

TCON.CONST is set to be 1.55 and TC.NPOW is –1.33. Atlas affords an accurate numerical simulation to predict the temperature distribution in a 3D structure. The typical LDMOS has an output power of 0.7 W per mm of gate width. Assume the device efficiency is 60%, the heat source is easily computed to be 0.1867W for the 400 μm finger width device.

Simulation results of the temperature distribution across the top surface are shown in

A 9-finger device model is further simulated for thermal distribution research. Each finger represents the two adjacent LDD regions which mean the thermal source area. The space between each finger is mainly pitch s area.

A bell-like temperature distribution is obviously appeared in the device, show in

To make the temperature rolling down, structure modification can be an option way to improve the device thermal performance. In our research work, the structure is

modified with different die thickness, pitch S length and finger width. According to the present process level, output power density is assumed to change from 0.6 W/mm to 1 W/mm, with a step of 0.1 W/mm. We trace the highest temperature changes with all these structure modifications and the results are shown in Figures 4-6.

pitch S length. The trend follows a reasonable way that large S area has a lower temperature. This can be easily understood for the large area of heat dissipation and thermal contact. Increasing the pitch length causes the device occupying a larger area and it’s not benefit for circuit designers. In our study, the longest pitch S is considered to be 40 μm. Variation is changed from 25 μm to 40 μm with a step of 5 μm and the die thickness and finger width remain at the typical value. The highest temperature reaches up to 317.55 K and it can be reduced by 3.88 K with an increase of 15 μm on pitch s length. For the 0.6 W/mm device considered, the highest temperature 310.33 K can also be reduced by 2.33 K, accounting for 22%. This ratio is almost the same as in the 1 W/mm device. Increasing the pitch S area is another optional approach to reduce the temperature. Besides, it’s much easier for technology processing.

Increasing the finger width may introduce more parasitic capacity, but at the same time, it can afford more power output. So, the study of temperature change with different finger width is also important.

The above three structure study has found the thinner die thickness and larger pitch area have benefit for thermal especially at high output power density. To further figure out these two factors affection, we study the simulation with different combinations. A 1 W/mm device is selected to complete the temperature variation. A more obvious temperature change appears in

To give instructions for device designer, a temperature study on LDMOS with different die thickness, pitch S length and finger width is presented in this work. Temperature distribution is obtained with the numerical me thod integrated in Silvaco. The simulation results indicate a 44% and 22% temperature reduction with modifycation on die thickness and pitch S length respectively. Increasing the finger width, on contrast, has no advantage for cooling down the temperature. For a device with 1 W/mm output power density, the most effective combination with 40 μm die thickness and 40 μm pitch S length, the highest temperature drops by 55%.

This work was supported by the IEB ES 64330 for Thermo-Electric Generator, funded by Vinnova FFI program.