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S. Lin, Y.-B. Kim and F. Lombardi, “Design and Analysis of a 32 nm PVT Tolerant CMOS SRAM Cell for Low Leakage and High Stability,” Integration the VLSI Journal, Vol. 43, No. 2, 2010, pp. 176-187. doi:10.1016/j.vlsi.2010.01.003

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