Article citationsMore>>

Heo, S.I., Kahng, A.B., Kim, M., Wang, L. and Yang, C. (2019) Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI. 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, 25-29 March 2019, 830-835.
https://doi.org/10.23919/DATE.2019.8715096

has been cited by the following article:

Follow SCIRP
Twitter Facebook Linkedin Weibo
Contact us
+1 323-425-8868
customer@scirp.org
WhatsApp +86 18163351462(WhatsApp)
Click here to send a message to me 1655362766
Paper Publishing WeChat
Free SCIRP Newsletters
Copyright © 2006-2024 Scientific Research Publishing Inc. All Rights Reserved.
Top