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http://dx.doi.org/10.1109/ccece.2014.6901052

has been cited by the following article:

• TITLE: On the Production Testing of Memristor Ratioed Logic (MRL) Gates

  AUTHORS: Ahmed Shukry Emara, Ahmed Hassan Madian, Hassanein Hamed Amer, Sherif Hassanein Amer, Mohamed Bakr Abdelhalim

  KEYWORDS: Memristors, MRL, Production Testing, Fault Model, Fault Coverage

  JOURNAL NAME: Circuits and Systems, Vol.7 No.10, August 18, 2016

  ABSTRACT: This paper focuses on the production testing of Memristor Ratioed Logic (MRL) gates. MRL is afamily that uses memristors along with CMOS inverters to design logic gates. Two-input NAND andNOR gates are investigated using the stuckat fault model for the memristors and the five-faultmodel for the transistors. Test escapes may take place while testing faults in the memristors.Therefore, two solutions are proposedto obtain full coverage for the MRL NAND and NOR gates. The first is to apply scaled input voltages and the second is to change the switching threshold of the CMOS inverter. In addition, it is shown that test speed and order should be taken into consideration. It is proven that three ordered test vectors are needed for full coverage in MRL NAND and NOR gates, which is different from the order required to obtain 100% coverage in the conventional NAND and NOR CMOS designs.