Y. N. Chang, H. Suzuki, and K. K. Parhi, “A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder,” IEEE Journal on Solid-State Circuits, Vol. 35, No. 6, pp. 826–834, June 2000.

has been cited by the following article:

• TITLE: A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering

  AUTHORS: C. ARUN, V. RAJAMANI

  KEYWORDS: Viterbi Decoder, Convolutional Codes, High-Speed, Low Power Consumption, Parallel Processing, Deep Pipelining

  JOURNAL NAME: International Journal of Communications, Network and System Sciences, Vol.2 No.6, September 22, 2009

  ABSTRACT: A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.