Y. Yin, H. Klar and P. Wennekers, “A Cascade 3-1-1 Multibit ΣΔ Modulator with Reduced Sensitities to Non-Idealities,” The IEEE International Symposium on Circuits and Systems, Vol. 4, 2005, pp. 3087-3090.

has been cited by the following article:

• TITLE: Behavioral Modeling and Simulation of Cascade Multibit ΣΔ Modulator for Multistandard Radio Receiver

  AUTHORS: Sonia Zouari, Houda Daoud, Mourad Loulou, Patrick Loumeau, Nouri Masmoudi

  KEYWORDS: ΔΣ ADC; Multistandard; VHDL-AMS Language; Behavioural Simulation

  JOURNAL NAME: Circuits and Systems, Vol.4 No.1, January 28, 2013

  ABSTRACT: In this paper, a cascade Sigma-Delta (ΣΔ) Analog to Digital Converter (ADC) for multistandard radio receiver was presented. This converter is supposed to be able to support GSM, UMTS, Wifi and WiMAX communication standards. The Sigma-Delta modulator makes use of 4 bit quantizer and Data-Weighted-Averaging (DWA) technique to attain high linearity over a wide bandwidth. A top-down design methodology was adopted to provide a reliable tool for the design of reconfigurable high-speed ΣΔMs. VHDL-AMS language was used to model the analog and mixed parts of the selected 2-1-1 cascade ΣΔ converter and to verify their reconfiguration parameters based on behavioural simulation. This multistandard architecture was high level sized to adapt the modulator performance to the different standards requirements. The effects of circuit non-idealities on the modulator performance were modeled and analyzed in VHDLAMS to extract the required circuit parameters.