Rahman, A., et al. (2013) Reliability Studies of a 22 nm SoC Platform Technology Featuring 3-D Tri-Gate, Optimized for Ultra Low Power, High Performance and High Density Application. 2013 IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, 14-18 April 2013, PI.2.1-PI.2.6.
https://doi.org/10.1109/IRPS.2013.6532105

has been cited by the following article:

• TITLE: 28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part II

  AUTHORS: Ali Mohsen, Adnan Harb, Nathalie Deltimple, Abraham Serhane

  KEYWORDS: UTBB FD-SOI: Ultra-Thin Body and Box Fully Depleted Silicon on Insulator, Tri-Gate FinFET, DIBL: Drain Induced Barrier Lowering

  JOURNAL NAME: Circuits and Systems, Vol.8 No.5, May 19, 2017

  ABSTRACT: This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.