Thapliyal, H. and Srinivas, M.B. (2004) High Speed Efficient N × N Bit Parallel Hierarchical Overlay Multiplier Architecture Based on Ancient Indian Vedic Mathematic. Transactions on Engineering, Computing and Technology, 2, 225-228.

has been cited by the following article:

• TITLE: Design and Implementation of an Efficient Reversible Comparator Using TR Gate

  AUTHORS: Subramanian Saravanan, Ila Vennila, Sudha Mohanram

  KEYWORDS: Reversible Logic Gates, Reversible Logic Circuits, (Very Large Scale Integration) VLSI Design

  JOURNAL NAME: Circuits and Systems, Vol.7 No.9, July 27, 2016

  ABSTRACT: Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computing, etc. In industrial automation, comparators play an important role in segregating faulty patterns from good ones. In previous works, these comparators have been implemented with more number of reversible gates and computational complexity. All these comparators use propagation technique to compare the data. This will reduce the efficiency of the comparators. To overcome the problem, this paper proposes an efficient comparator using (Thapliyal Ranganathan) TR gate utilizing full subtraction and half subtraction algorithm which will improve the computation efficiency. The comparator design using half subtraction algorithm shows an improvement in terms of quantum cost. The comparator design using full subtraction algorithm shows effectiveness in reducing number of reversible gates required and garbage output.