Schinkel, D., Mensink, E., Klumperink, E.A., Van Tuijl, E. and Nauta, B. (2009) Low-Power, High-Speed Transceivers for Network-on-Chip Communication. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17, 12-21.
http://dx.doi.org/10.1109/TVLSI.2008.2001949

has been cited by the following article:

• TITLE: VELAN: Variable Energy Aware Sense Amplifier Link for Asynchronous Network on Chip

  AUTHORS: Erulappan Sakthivel, Veluchamy Malathi, Muruganantham Arunraja

  KEYWORDS: Network-on-Chip (NoC), Double Tail Sense Amplifier (DTSA), Clock Gating (CG)

  JOURNAL NAME: Circuits and Systems, Vol.7 No.3, March 31, 2016

  ABSTRACT: A real time multiprocessor chip paradigm is also called a Network-on-Chip (NoC) which offers a promising architecture for future systems-on-chips. Even though a lot of Double Tail Sense Amplifiers (DTSA) are used in architectural approach, the conventional DTSA with transceiver exhibits a difficulty of consuming more energy and latency than its intended design during heavy traffic condition. Variable Energy aware sense amplifier Link for Asynchronous NoC (VELAN) is designed in this research to eliminate the difficulty, which is the combination of Variable DTSA circuitry (V-DTSA) and Transceiver. The V-DTSA circuitry has following components such as bootable DTSA (B-DTSA) and bootable clock gating DTSA (BCG-DTSA), Graph theory based Traffic Estimator (GTE) and controller. Depending upon the traffic rate, the controller activates necessary DTSA modules and transfers information to the receiver. The proposed VELAN design is evaluated on TSMC 90 nm technology, showing 6.157 Gb/s data rate, 0.27 w total link power and 354 ps latency for single stage operation.