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has been cited by the following article:

• TITLE: An 8 Bit 0.8 GS/s 8.352 mW Modified Successive Approximation Register Based Analog to Digital Converter in 65 nm CMOS

  AUTHORS: Ananthanarayanan Parthasarathy

  KEYWORDS: Moving Binary Search Tree, SAR-ADC, Low Power

  JOURNAL NAME: Circuits and Systems, Vol.6 No.12, December 30, 2015

  ABSTRACT: We propose a new approach in reducing the power consumption of the successive approximation register Analog to Digital Converter (SAR-ADC) by changing the convergence algorithm of the Digital to Analog converter (DAC) input of the SAR-ADC. Different search algorithms such as binary search tree, moving binary search tree (BST), least significant bit shifter (LSB), adaptive algorithm and split-register moving BST algorithm are designed and analyzed for faster convergence of the DAC input. In this paper, we design a 0.8 GS/s, 8 bit (Effective number of bits (ENOB)—7.42), 8.352 mW SAR ADC with a proposed moving BST algorithm in 65 nm CMOS which ranks amongst the current state of the art ADCs with a FOM 65.25 fJ/step.