Design of Low Power Comparator Using DG Gate

Bahram Dehghan, Abdolreza Roozbeh, Jafar Zare

Department of Electrical Engineering, Sarvestan Branch, Islamic Azad University, Sarvestan, Iran.
Department of Electrical Engineering, Zarghan Branch, Islamic Azad University, Zarghan, Iran.
Young Researchers and Elite Club, Sarvestan Branch, Islamic Azad University, Sarvestan, Iran.

DOI: 10.4236/cs.2014.51002                

Abstract

In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. In the present paper, we show a design of the reversible comparator based on the quantum gates implementation of the reversible DG gate. The reversible DG gate is designed by using 3 × 3 quantum gates such as NOT, CNOT, Controlled-V and Controlled-V⁺ gates. Also, we have used the TR gate and various types of quantum gates in the implementation results. Low power three-bit comparator is designed using DG Gate, New Gate and Fredkin Gate. In order to evaluate the benefit of using the DG gate proposed in this paper, one-bit comparator is constructed. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator.

Keywords

Reversible Logic Comparator; TR and DG Gate; Quantum Cost; Garbage Output

Conflicts of Interest

The authors declare no conflicts of interest.

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