Electronically-Controllable Grounded-Capacitor-Based Grounded and Floating Inductance Simulated Circuits Using VD-DIBAs ()
1. Introduction
The importance of grounded and floating simulated inductors in the context of active network synthesis is well known [1]. Several grounded and floating inductance simulation schemes, employing different active elements such as operational amplifiers (op-amps) [2-6], current conveyors (CCs) [7-15], current controlled conveyors (CCCIIs) [16,17], current feedback operational amplifiers (CFOAs) [18,19], operational mirrored amplifiers (OMAs) [20], differential voltage current conveyors (DVCCIIs) [21], current differencing buffered amplifiers (CDBAs) [22,23], current differencing transconductance amplifiers (CDTAs) [24,25], operational transconductance amplifiers (OTAs) [26,27] have been reported in the literature. In [28], many new active building blocks have been introduced; VD-DIBA is one of them. Till now, some applications of VD-DIBAs have been reported in the open literature such as in the realization of all pass filters [29], realization of grounded and floating inductance circuits using two/three VD-DIBAs as reported in [30], electronically controllable sinusoidal oscillator in [31] and voltage-mode universal biquad in [32,33]. The purpose of this paper is to introduce new VD-DIBA-based: 1) a lossless grounded inductor using only a single VD-DIBA, one resistor and a grounded capacitor without requiring any matching condition and 2) two floating inductance simulation circuits employing two VD-DIBAs, one resistor and a grounded capacitor along with a single matching condition for floatation. The genesis of these FI circuits is inspired by [1,34,35].
2. The Proposed New Configuration
The schematic symbol and equivalent model of the VDDIBA (−) are shown in Figures 1(a) and (b) respectively [29]. The model of VD-DIBA (−) includes two controlled sources: the current source controlled by differential voltage
, with the transconductance gm, and the voltage source controlled by differential voltage
, with the unity voltage gain. The VD-DIBA (−) can be described by the following set of equations:
(a)
(b)
Figure 1. (a) Schematic symbol (b) equivalent model of VDDIBA.
Figure 2. Proposed grounded inductance simulation configuration.
(1)
The proposed grounded and floating inductance circuits are shown in Figure 2 and Figure 3 respectively.
A routine analysis of the circuit shown in Figure 2 results in the following expression for the input impedance
(2)
The circuit, thus, simulates a grounded inductance with the inductance value given by
(3)
(a)
(b)
Figure 3. Proposed floating inductance simulation configurations.
On the other hand, analysis of the new FI circuits shown in Figures 3(a) and (b) yields
(4)
which proves that the circuits simulate a floating lossless inductance with the inductance value given by
(5)
The proposed CMOS implementation of VD-DIBA (−) is shown in Figure 4. The CMOS VD-DIBA (−) is implemented using 0.35 µm MIETEC real transistor model which are listed in Table 1. Aspect ratios of transistors used are given in Table 2.
3. Non-Ideal Analysis and Sensitivity Performance
Let Rz and Cz denote the parasitic resistance and parasitic capacitance of the Z-terminal. Taking into account the non-idealities of the VD-DIBA (−), namely 
, where 
and 
are voltage tracking errors of the VD-DIBA, for the circuit shown in Figure 2, the nonideal input impedance is found to be
Figure 4. Proposed CMOS Implementation of VD-DIBA, VDD = −VSS = 2 V, VB1 = −0.44 V, VB2 = IB3 = −0.22 V and VB4 = −0.9 V.
Table 2. Dimensions of CMOS transistors.
(6)
From the above, a non-ideal equivalent circuit of the grounded inductor is derivable which is shown in Figure 5.
Where
,
, 
, and 
From the above, the sensitivities of L with respect to various active and passive elements are found to be
(7)
similarly, for the circuit shown in Figures 3(a) and (b) for
, the input-output currents and voltages relationships are given by:
(8)
The non-ideal equivalent circuit of floating inductors of Figures 3(a) and (b) derivable from Equation (8) is shown in Figure 6.
Where 
and 
The various sensitivities of L with respect to active and passive elements are:
(9)
Taking
, 
, 
, 
and
, these sensitivities are found to be (1, 0, 1, 0, 0, −1) and (1, 0, −1, −1, 0, 0) for Equations (7) and (9) respectively. Thus,
Figure 7. Band pass filter realized by the new grounded simulated inductor.
all the passive and active sensitivities of both grounded and floating inductance circuits are low.
4. Simulation Results of the New Proposed Grounded/Floating Inductance Configurations
The workability of the proposed simulated inductors has been verified by realizing a band pass filter (BPF) as shown in Figures 7 and 8.
The transfer function realized by this configuration is given by
(10)
from where it is seen that bandwidth and centre frequency are independently tunable, the former by R2 and the latter by any of R1, 
and C1.
The transfer function realized by configuration shown in Figure 8 is given by
(11)
In this case, bandwidth is tunable by R1 whereas centre frequency can be tuned by C1.
Performance of the new simulated inductors was verified by SPICE simulations. CMOS-based VD-DIBA (−) (as shown in Figure 4) was used to determine the frequency responses of the grounded and floating simulated inductors. The following values were used for grounded inductor: C1 = 0.01nF, R1 = 100 kΩ,
and for the floating inductor: C0 = 0.01 nF, R0 = 100 kΩ, 
,
. From the frequency response of the simulated grounded inductor (Figure 9) it has been observed that the inductance value remains constant up to 1 MHz. Similarly, from the frequency response of the simulated floating inductor (Figure 10) the inductance value also remains constant up to 1 MHz.
To verify the theoretical analysis of the application circuits shown in Figures 7 and 8, they have also been simulated using CMOS-based VD-DIBA (−) as shown in Figure 4. The component values used were for Figure 7: C1 = 0.1 nF, C2 = 1 pF, R1 = 100 kΩ, R2 = 113.258 kΩ and for Figures 8(a) and (b): C0 = 0.1 nF, C1 = 0.01 nF, R0 = 100 kΩ, R1 = 71.652 kΩ, 
(which can be maintained by taking VB1 = −1.5V). The VDDIBA was biased with ±2 volts D.C. power supplies with VB1 = −0.44V, VB2 = VB3 = −0.22V and VB4= −0.9V. VD-DIBA (−) transconductance is controlled by VB1. Figure 11, Figures 12(a) and (b) show the simulated filter responses of the BP filters.
The above described results, thus, confirm the validity of the application of the proposed grounded and floating simulated inductance circuits. A comparison of the various salient features of the proposed configurations as compared to other previously known grounded and FI
(a)
(b)
Figure 8. Band pass filters realized by the new floating simulated inductors of Figures 3(a) and (b).
Figure 9. Frequency response of the simulated grounded inductor.
Figure 10. Frequency response of the simulated floating inductor.
Figure 11. Frequency response of BPF using the proposed simulated grounded inductor.
(a)
(b)
Figure 12. Frequency response of BPF using the proposed simulated floating inductor.
Table 3. Comparison with other previously published grounded and floating inductors.
simulators has been included in Table 3.
5. Conclusions
New circuits of lossless grounded and floating inductance have been proposed employing VD-DIBAs. The proposed grounded inductance circuit employs only one VD-DIBA (−), one resistor and one grounded capacitor and does not require any component matching condition. On the other hand, the two floating inductance configurations each using two VD-DIBAs (−), one resistor and one grounded capacitor, need only a single realization condition for floatation. The SPICE simulation results have confirmed the workability of the new propositions as well as the suggested application examples using them.
The problem of realizing any new single VD-DI-BAbased FI configuration using a single grounded capacitor and without requiring any matching condition appears to be an interesting problem which is open to be investigated.
6. Acknowledgements
The authors gratefully acknowledge Prof. Dr. Raj Senani, Head, Division of Electronics and Communication Engineering, and Director NSIT, New Delhi, for useful discussions/suggestions.
NOTES