High Speed Digital Oscillator Implementations Based on Advanced Arithmetic and Architecture Techniques


The advances of digital arithmetic techniques permit computer designers to implement high speed application specific chips. The currently produced digital circuits have demonstrated high performance in terms of several criteria, such as, high clock rate, short input/output delay, small silicon area, and low power dissipation. In this paper, we implement several sinusoidal generation methods to optimize their performance and output using advanced digital arithmetic techniques. In this paper, the implementations of advanced digital oscillator structures with and without pipelining are proposed. The synthesis results of the implementation with pipelining have proven that it is superior to other sinusoidal generation methods in terms of the maximum frequency and signal resolution. Hence, this method is used in the design of the proposed digital oscillator chip.

Share and Cite:

Shatnawi, A. and Shatnawi, M. (2013) High Speed Digital Oscillator Implementations Based on Advanced Arithmetic and Architecture Techniques. Circuits and Systems, 4, 252-263. doi: 10.4236/cs.2013.43034.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] M. Schanerberger and S. S. Awad, “The Implementation of a Digital Sine Wave Oscillator Using the TMS320C25: Distortion Reduction and Applications,” IEEE Transactions on Instrumentation and Measurement, Vol. 39, No. 6, 1990, pp. 870-873. doi:10.1109/19.65786
[2] M. Al-Ibrahim, S. Bataineh and A. Al-Khateeb, “Digital Sinusoidal Oscillators with High Frequency Resolution and Low Harmonic Distortion,” International Journal of Electronics, Vol. 87, No. 10, 2000, pp. 1209-1218. doi:10.1080/002072100415657
[3] A. I. Abu-El-Haija and M. M. Al-Ibrahim, “Improving Performance of Digital Sinusoidal Oscillators by Means of Error Feedback Circuits,” IEEE Transactions on Circuits and Systems, Vol. 33, No. 4, 1986, pp. 373-380. doi:10.1109/TCS.1986.1085932
[4] N. J. Fliege and J. Wintermantel, “Complex Digital Oscillators and FSK Modulators,” IEEE Transactions on Signal Processing, Vol. 40, No. 2, 1992, pp. 333-342. doi:10.1109/78.124943
[5] M. M. Al-Ibrahim and A. M. Al-Khateeb, “Efficient Low Frequency Digital Sinusoidal Oscillator,” International Journal of Electronics, Vol. 81, No. 2, 1996, pp. 159-169. doi:10.1080/002072196136823
[6] M. M. Al-Ibrahim and A. M. Al-Khateeb, “Digital Sinusoidal Oscillator with Low and Uniform Frequency Spacing,” IEE Proceedings of Circuits, Devices and Systems, Vol. 144, No. 3, 1997, pp. 185-189. doi:10.1049/ip-cds:19971004
[7] M. M. Al-Ibrahim and A. M. Al-Khateeb, “Extremely Low Sensitivity Digital Sinusoidal Oscillator Structure,” International Journal of Electronics, Vol. 85, No. 6, 1998, pp. 755-765. doi:10.1080/002072198133806
[8] A. A. Hiasat and A. M. Al-Khateeb, “New High-Resolution Digital Sinusoidal Oscillator Structure with Extremely Low Frequency and Sensitivity,” International Journal of Electronics, Vol. 86, No. 3, 1999, pp. 287-296. doi:10.1080/002072199133427
[9] M. M. Al-Ibrahim (Jarrah), “A Multi Frequency Range Digital Sinusoidal Oscillator with High Resolution and Uniform Frequency Spacing,” IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, Vol. 48, No. 9, 2001, pp. 872-876.
[10] M. M. Al-Ibrahim, “A New Hardware-Efficient Digital Sinusoidal Oscillator with Lowand Uniform-Frequency Spacing,” Electrical Engineering, Vol. 85, No. 5, 2003 pp. 255-260. doi:10.1007/s00202-003-0168-4
[11] M. D. Ercegovac and T. Lang, “Digital Arithmetic,” Morgan Kaufmann Publishers, Burlington, 2003.
[12] C. K. Koc, “Parallel Canonical Recording,” Electronics Letters, Vol. 32, No. 22, 1996, pp. 2063-2065. doi:10.1049/el:19961402
[13] A. D. Booth. “A Signed Binary Multiplication Technique,” Quarterly Journal of Mechanics and Applied Mathematics, Vol. 4, No. 2, 1951, pp. 236-240. doi:10.1093/qjmam/4.2.236
[14] C. S. Wallace, “A Suggestion for a Fast Multiplier,” IEEE Transactions on Electronic Computers, Vol. 13, No. 2, 1964, pp. 14-17. doi:10.1109/PGEC.1964.263830
[15] D. Villeger and V. G. Oklobdzija, “Evaluation of Booth Encoding Techniques for Parallel Multiplier Implementation,” Electronics Letters, Vol. 29, No. 23, 1993, pp. 2016-2017. doi:10.1049/el:19931345
[16] V. G. Oklobdzija and D. Villeger, “Improving Multiplier Design by Using Improved Column Compression Tree and Optimized Final Adder in CMOS Technology,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 3, No. 2, 1995, pp. 292-301.
[17] V. G. Oklobdzija, D. Villeger and S. S. Liu, “A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach,” IEEE Transactions on Computers, Vol. 45, No. 3, 1996, pp. 294-306. doi:10.1109/12.485568
[18] P. F. Stelling and V. G. Oklobdzija, “Optimal Circuits for Parallel Multipliers,” IEEE Transactions on Computers, Vol. 47, No. 3, 1998, pp. 273-285. doi:10.1109/12.660163
[19] A. Weinberger and J. L. Smith, “A Logic for High-Speed Addition,” National Bureau of Standards Circulation, Vol. 591, 1958, pp. 3-12.
[20] A. Weinberger, “4:2 Carry-Save Adder Module,” IBM Technical Disclosure Bulletin, Vol. 23, No. 8, 1981, pp. 3811-3814.
[21] D. Villeger and V. G. Oklobdzija, “Analysis of Booth Encoding Efficiency in Parallel Multipliers Using Compressors for Reduction of Partial Products,” 1993 Conference Record of The Twenty-Seventh Asilomar Conference on Signals, Systems and Computers, Vol. 1, 1993, pp. 781-784.
[22] P. J. Ashenden, “The VHDL Cookbook,” Department of Computer Science, University of Adelaide, 1990.
[23] U. Heinkel, M. Padeffke, W. Haas, T. Buerner, H. Braisz, T. Gentner and A. Grassmann, “The VHDL Reference: A Practical Guide to Computer-Aided Integrated Circuit Design Including VHDL-AMS,” Wiley, Chichester, 2000.
[24] Introduction to ModelSim Simulation Software Tool. http://www.model.com/
[25] Introduction to Xilinx Synthesize Software Tool. http://www.xilinx.com/
[26] D. A. Patterson and J. L. Hennessy, “Computer Organization and Design: The Hardware/Software Interface,” 3rd Edition, Morgan Kaufmann Publishers, Burlington, 2004.
[27] J. L. Hennessy and D. A. Patterson, “Computer Architecture: A Quantitative Approach,” 3rd Edition, Morgan Kaufmann Publishers (Elsevier), Burlington, 2002.

Copyright © 2024 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.