A Novel Time Domain Noise Model for Voltage Controlled Oscillators

Li Ke, Peter Wilson, Reuben Wilcock

Electronics and Computer Science, University of Southampton, Southampton, UK.

DOI: 10.4236/cs.2013.41015                

Abstract

This paper describes a novel time domain noise model for voltage controlled oscillators that accurately and efficiently predicts both tuning behavior and phase noise performance. The proposed method is based on device level flicker and thermal noise models that have been developed in Simulink and although the case study is a multiple feedback four delay cell architecture it could easily be extended to any similar topology. The strength of the approach is verified through comparison with post layout simulation results from a commercial simulator and measured results from a 120 nm fabricated prototype chip. Furthermore, the effect of control voltage flicker noise on oscillator output phase noise is also investigated as an example application of the model. Transient simulation based noise analysis has the strong advantage that noise performance of higher level systems such as phase locked loops can be easily determined over a realistic acquisition and locking process yielding more accurate and reliable results.

Keywords

Voltage Controlled Oscillators; Noise Model; Simulation

Conflicts of Interest

The authors declare no conflicts of interest.

References

[1]	Z. H. Gao, Y. C. Li and S. L. Yan, “A 0.4 ps-RMS-Jitter 1-3 GHz Ring Oscillator PLL Using Phase-Noise Preamplification,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 9, 2008, pp. 2079-2089. doi:10.1109/JSSC.2008.2001873
[2]	G. Manganaro, S. UngKwak, S. H. Cho and A. Pulincherry, “A Behavioral Modelling Approach to the Design a Low Jitter Clock Source,” IEEE Transactions on Circuit and Systems II, Vol. 50, No. 11, 2003, pp. 804-814.
[3]	L. Bizjak, N. Da Dalt, P. Thurner, R. Nonis, P. Paletri and L. Selmi, “Comprehensive Behavioral Modeling of Conventional and Dual-Tunig PLLs,” IEEE Transactions on Circuit and System I, Vol. 55,No. 6, 2008, pp. 1628-1638.
[4]	S. Brigati, F. Francesconi, A. Malvasi, A. Pesucci and M. Polerri, “Modeling of Franctional-N Division Frequency Synthesizers with Simulink and Matlab,” The 8th IEEE International Conference on Electronics, Circuits and Systems, Vol. 2, 2001, pp. 1081-1084.
[5]	M. H. Perrott, “Fast and Accurate Behaviotal Simulation of Fractional-N Frequency Synthesizers and Other PLL/DLL Circuits,” Proceedings of the 39th annual Design Automation Conference, New York, 10-14 June 2002, pp. 498-503.
[6]	R. B. Staszewski, C. Fernando and P. T. Balsara, “Event-Driven Simulation and Modeling of Phase Noise of an RF Oscillator,” IEEE Transactions on Circuit and Systems I, Vol. 52, No. 4, 2005, pp. 723-733.
[7]	D. A. Badillo and S. Kiaei, “A Low Phase Noise 2.0 V 900 MHz CMOS Voltage Controlled Ring Oscillator,” Proceedings of the 2004 International Symposium on Circuits and Systems, Vol. 4, 2004, p. 533
[8]	K. Li, R. Wilcock and P. Wilson, “Improved 6.7 GHz CMOS VCO Delay Cell with up to Seven Octave Tuning Range,” IEEE International Symposium on Circuits and Systems, Seattle, 18-21 May 2008, pp. 444-447.
[9]	R. J. Baker, “CMOS Circuit Design, Layout and Simulation,” 2nd Edition, IEEE Press, Wiley, Hoboken, 2008. doi:10.1109/9780470547106
[10]	A. A. Abidi, “Phase Noise and Jitter in CMOS Ring Oscillators,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 8, 2006, pp. 1803-1816. doi:10.1109/JSSC.2006.876206
[11]	S. C. Terry, J. Blalock, J. M. Rochelle, M. N. Ericson and S. D. Caylor, “Time-Domain Noise Analysis of Lineat Time-Invariant and Linear Time-Variant Systems Using MATLAB and HSPICE,” IEEE Transactions on Nuclear Science, Vol. 52, No. 3, 2005, pp. 1418-1422.