Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits


This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.

Share and Cite:

S. Rai, R. Mishra and S. Tiwari, "Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits," Circuits and Systems, Vol. 4 No. 1, 2013, pp. 20-28. doi: 10.4236/cs.2013.41005.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] A. Tajalli and Y. Leblebici, “Leakage Current Reduction Using Sub-Threshold Source-Coupled Logic,” IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 56, No. 5, 2009, pp. 374-378.
[2] A. Tajalli, E. J. Brauer, Y. Leblebici and E. Vittoz, “Sub-Threshold Source-Coupled Logic Circuits for Ultra-Low Power Applications,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 7, 2008, pp. 1699-1710. doi:10.1109/JSSC.2008.922709
[3] D. Suvakovic and C. A. T. Salama, “A Low Vt CMOS Implantation of an LPLV Digital Filter Core for Portable Audio Applications,” Transactions on Circuits Systems, II: Analog and Digital Signal Processing, Vol. 47, No. 11, 2000, pp. 1297-1300.
[4] G. Gielen, “Ultra-Low-Power Sensor Networks in Nanometer CMOS,” International Symposium on Signals, Circuits and Systems, Vol. 1, Iasi, 13-14 July 2007, pp. 1-2. doi:10.1109/ISSCS.2007.4292635
[5] B. A. Warneke and K. S. J. Pister, “An Ultra-Low Energy Microcontroller for Smart Dust Wireless Sensor Networks,” IEEE International Solid-State Circuits Conference, Vol. 1, 2004, pp. 316-317.
[6] L. S. Wong, et al., “A Very Low-Power CMOS Mixed-Signal IC for Implantable Pacemaker Applications,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, 2004, pp. 2446-2456. doi:10.1109/JSSC.2004.837027
[7] E. Vittoz, “Weak Inversion for Ultimate Low-Power Logic,” In: C. Piguet, Ed., Low-Power Electronics Design, CRC Press, Boca Raton, 2005.
[8] B. H. Calhoun, A. Wang and A. Chandrakasan, “Modeling and Sizing for Minimum Energy Operation in Sub-Threshold Circuits,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 9, 2005, pp. 1778-1786. doi:10.1109/JSSC.2005.852162
[9] M. Anis and M. Elmasry, “Multi-Threshold CMOS Digital Circuits, Managing Leakage Power,” Kluwer, Norwell, 2003. doi:10.1007/978-1-4615-0391-0
[10] E. Brauer and Y. Leblebici, “Semiconductor Based High-Resistance Device and Logic Application,” European Patent Application No. 07104895.3-1235, 2007.
[11] H. Soeleman, K. Roy and B. C. Paul, “Robust Subthreshold Logic for Ultra Low Power Operation,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 1, 2001, pp. 90-99.
[12] F. Cannillo and C. Toumazou, “Nano-Power Sub-Threshold Current-Mode Logic in Sub-100 nm Technologies,” IEEE Electronics Letters, Vol. 41, No. 23, 2005, pp. 1268-1269. doi:10.1049/el:20053082
[13] A. Tajalli, E. Vittoz, Y. Leblebici and E. J. Brauer, “Ultra Low Power Sub-Threshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept,” Proceedings of the European Solid-State Circuit Conference, Munich, September 2007, pp. 281-284.
[14] M. Horowitz, T. Indermaur, R. Gonzalez, et al., “Low-Power Digital Design,” Proceedings of IEEE International Symposium on Low Power Electronics and Design, San Diego, 10-12 October 1994, pp. 8-11.
[15] http://www.cadence.com/.

Copyright © 2023 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.