New Approach for Hardware/Software Embedded System Conception Based on the Use of Design Patterns


This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.

Share and Cite:

Y. Manai, J. Haggège and M. Benrejeb, "New Approach for Hardware/Software Embedded System Conception Based on the Use of Design Patterns," Journal of Software Engineering and Applications, Vol. 3 No. 6, 2010, pp. 525-535. doi: 10.4236/jsea.2010.36060.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] R. C. Dorf, “Systems, Controls, Embedded Systems, Energy, and Machines,” Taylor & Francis, New York, 2006, pp. 486-511.
[2] K. Virk and J. Madsen, “A System-Level Multiprocessor System-on-Chip Modeling Framework,” Proceedings of SOC, 2004.
[3] A. D. Pimentel and C. Erbas, “A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels,” IEEE Transactions on Computer, Vol. 55, No. 2, February 2006, pp. 99-112.
[4] B. Zhou, W. Qiu and C. Peng, “An Operaing System Framework for Reconfigurable Systems,” Proceedings of CIT, Salt Lake, 2005.
[5] S. Pasricha, N. Dutt and M. B. Romdhane, “Using TLM for Exploring Bus-Based SoC Communication Architec- tures,” Proceedings of ASAP, Atlantic, 2005.
[6] R. Cumplido, S. Jones, R. M. Goodall and S. Bateman, “A High Performance Processor for Embedded Real-Time Control,” IEEE Transactions on Control Systems Tech- nology, Vol. 13, No. 3, May 2005, pp. 485-492.
[7] X. Wu, V. A. Chouliaras, J. L. Nunez and R. M. Goodall, “A Novel DS Control System Processor and its VLSI Implem-Entation,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 3, March 2008, pp. 217-228.
[8] D. L. Sancho-Pradel and R. M. Goodall, “Targeted Processing for Real-Time Embedded Mechatronic Sys- tems,” Control Engineering Practice, Vol. 15, 2007, pp. 363-375.
[9] Y. Atat and N. E. Zergainoh, “Automatic Code Generation for MPSoC Platform Starting From Simulink/Matlab: New Approach to Bridge the Gap between Algorithm and Architecture Design,” Conference of ICTTA, Bali Island, 2008.
[10] G. Wang, W. Gong and R. Kastner, “Application Parti- tioning on Programmable Platforms Using the Ant Colony Optimization,” Journal of Embedded Computing, Vol. 2, No. 1, 2005, pp. 1-18.
[11] Y. Manai, J. Haggège and M. Benrejeb, “HW/SW Parti- tioning in Embedded System Conception Using Design Pattern Approach,” Conference of JTEA, Hammamet, 2008.
[12] K. B. Chehida, “Méthodologie de Partitionnement Logi- ciel/Matériel Pour Plateformes Reconfigurables Dynami- Quement,” PhD Thesis, Université de Nice-Sophia Anti- polis, France, 2004.
[13] E. Gamma, et al., “Design Patterns: Elements of Reusable Object-Oriented Software,” Addison-Wesley, Massachu- setts, 1995.
[14] S. Konrad, H. C. Cheng and L. A. Campbell, “Object Analysis Patterns for Embedded Systems,” IEEE Transac- tions on Software Engineering, Vol. 30, No. 12, December 2004, pp. 970-990.
[15] S. Konrad and B. Cheng, “Requirement Pattern for Embedded System,” Proceedings of the IEEE Joint Inter- national Conference on Requirements Engineering, Atlanta, 2002.
[16] R. Damasevicius, G. Majauskas and V. Stulikys, “Appli- cation of Design Patterns for Hardware Design,” Pro- ceedings of DAC, Anaheim, 2-6 June 2003, pp. 48-53.
[17] F. Rincon, F. Moya and J. Barba, “Model Reuse through Hardware Design Patterns,” Proceedings of Design, Automation, and Test in Europe, 2005.
[18] P. Coussy, et al., “Constrained Algorithmic IP Design for System-on-Chip,” Integration, the VLSI Journal, Vol. 40, No. 2, 2007, pp. 94-105.
[19] J. K. Mak, C. S. Choy and D. P. Lun, “Precise Modeling of Design Patterns in UML,” Proceedings of International Conference on Software Engineering, 2004.
[20] Y. Manai, J. Haggège and M. Benrejeb, “PI-Fuzzy Con- troller Conception with Design Pattern Based Approach,” 14th IEEE International Conference on Electronics, Cir- cuits and Systems, Marrakech, 2007, pp. 483-489.
[21] Y. Manai, “Contribution à la conception et la synthèse d’architecture de systèmes embarqués utilisant des plates- formes hétérogènes,” Ph.D. Dissertation, Ecole Nationale d’Ingénieurs de Tunis, Tunisia, 2009.

Copyright © 2023 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.