A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode Devices
Jin Young Choi
DOI: 10.4236/cn.2010.21002   PDF    HTML     8,480 Downloads   14,120 Views   Citations


For three fundamental input-protection schemes suitable for high-frequency CMOS ICs, which utilize protection devices such as NMOS transistors, thyristors, and diodes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit model of input HBM test environments for CMOS chips equipped with input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the peak voltage developed in the later stage of discharge, which corresponds to the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain strength and weakness of each protection scheme as an input ESD protection circuit for high-frequency ICs, and suggest valuable guidelines relating design of the protection devices and circuits.

Share and Cite:

Choi, J. (2010) A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode Devices. Communications and Network, 2, 11-25. doi: 10.4236/cn.2010.21002.

1. Introduction

CMOS chips are more vulnerable to electrostatic discharge (ESD) due to the thin gate oxides used, and therefore protection devices such as NMOS transistors are required at input pads. A large size for the protection devices is needed to reduce discharge current density and thereby to protect them against thermal-related problems. However, using the large devices adds parasitic capacitances to the input nodes to generate other problems such as gain reduction and poor noise characteristics in highfrequency ICs [1].

To reduce the added parasitics, various techniques have been suggested [1–3]. However, basic approaches should be to reduce the size of protection devices by utilizing, for example, thyristors or forward-biased diodes [4,5].

In this paper, we introduce three fundamental ESD protection schemes utilizing NMOS transistors, thyristors, and diodes, which can be implemented into input pad structures of high-frequency CMOS ICs, assuming usage of standard CMOS processes. While there can be many variants of the fundamental protection schemes, it is worthwhile to carefully examine the mechanisms leading to device failures when using the fundamental protection schemes since it can provide valuable information in designing most of protection circuits. We analyze and compare in detail discharge characteristics of the three protection schemes for various discharge modes in input human-body model (HBM) tests. A 2-dimensional device simulator, together with a circuit simulator, is utilized as a tool for a comparative analysis. The analysis methodology utilizing a device simulator has been widely adopted with credibility [6,7] since it can provide valuable information relating the mechanisms leading to device failure, which may not be obtained by measurements.

In Section 2, we suggest three protection device structures, which will be utilized for the comparative analysis, and introduce device characteristics based on DC device simulations, which will be utilized to confirm the mixedmode simulation results analyzed in Section 4. In Section 3, we briefly explain discharge modes in HBM tests and introduce the input protection circuits utilizing each suggested protection device. In Section 4, we construct an equivalent circuit model of a CMOS chip equipped with input protection devices to simulate various input HBM test situations, and execute mixed-mode transient simulations on the circuits including up to six active protection devices. We figure out weak modes, and present in-depth analysis results on critical characteristics such as peak voltages developed across gate oxides in input buffers, locations of peak temperature inside protection devices, and so on. In Section 5, we introduce AC device simulation results to compare magnitudes of the added parasitics when the suggested protection circuits are adopted. In Section 6, considerations relating device design are discussed.

2. Protection Device Structures and DC Characteristics

Figure 1 shows the NMOS protection device structure assumed in this work. The scales of two axes are in micrometers. The structure represents a conventional protection device incorporating n+ source and drain ESD implants, which is implied by the relatively deep junctions. In order to alleviate drain-contact melting problems caused by lattice heating, the gate-drain contact spacing is chosen to be 3.5μm, which can be considered as ordinary. Table 1 summarizes the principal structure parameters. The n+ and p+ junctions shown in Figure 1 are assumed to have Gaussian doping profiles with about 1020cm-3 of peak concentration.

The p+ junctions located at the upper left/right corners represent diffusions for substrate ground contacts. A series resistor of 1 MWμm, which is not shown in Figure 1, is connected at the bottom substrate node considering the distributed resistances leading to the substrate contacts located far away.

DC simulations were performed using a 2-dimensional device simulator ATLAS [8]. All necessary physical models including an impact ionization model were considered in the simulations. The latticeheating model included joule heat, generation-recombination heat, and Peltier-Thomson heat. The source, the gate, and the substrate were grounded, and the drain bias was varied for simulation.

Figure 2 shows the simulated drain current vs. voltage characteristics of the NMOS transistor in Figure 1 in a semi-log scale. We confirmed that a leakage current through the weakly inverted MOS channel dominates when the drain voltage is below 5V. Increasing the drain voltage, a leakage current through the reverse-biased n+-drain/p-sub junction starts to dominate, and the junction breakdowns by avalanche when the drain voltage is increased above 9.3V.

A generated hole current by avalanche flows to the substrate terminal to increase the body potential. With a sufficient hole current flowing, the body potential near the source junction gets high enough to forward-bias the n+-source/p-sub junction triggering a parasitic lateral npn (source/body/drain) bipolar transistor. The source, the body, and the drain act as an emitter, a base, and a collector, respectively. Generation of holes around the drain junction is augmented due to impact ionization caused by

Table 1. Principal parameters of the NMOS device

Table 2. Principal parameters of the lvtr_thyristor device

the injected electrons from the source, and thereby the required drain-source voltage is reduced to show a snapback, as indicated as ‘BJT trigger’ in Figure 2. After the snapback at about 9.4V, the drain-source voltage drops to about 4.6V of a bipolar holding voltage.

In Figure 2, a 2nd breakdown [9] occurs when the drain current is about 1.3mA/μm, and the required drain-source voltage is further reduced to cause device failures relating drain-contact melting in real devices. It was confirmed that the 2nd breakdown in Figure 2 occurs when the peak lattice temperature inside the device exceeds about 1, 100°K.

Figure 3 shows the lvtr_thyristor device structure assumed in this work. An lvtr_thyristor device is a pnpntype device suggested to the lower snapback voltage by incorporating a NMOS transistor into it [4]. The device in Figure 3 can be easily fabricated in standard CMOS processes, and does not incorporate ESD implant steps, which is implied by the relatively shallow junctions.

Table 2 summarizes the principal structure parameters. The n well is assumed to have a Gaussian doping profile with 1017cm-3 of peak concentration, and the doping profiles of the n+ and p+ junctions are similar to those of the p+ junctions in Figure 1. A series resistor is also connected at the bottom substrate node as in the NMOS device in Figure 1. The n+ and p+ anodes in Figure 3 are tied together to serve as an anode. The cathode, the gate, and the substrate were grounded, and the anode bias was varied for simulation.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] P. Leroux and M. Steyaert, “High-performance 5.2GHz LNA with on-chip inductor to provide ESD protection,” Electronics Letters, Vol. 37, pp. 467–469, March 2001.
[2] B. Kleveland, T. J. Maloney, I. Morgan, L. Madden, T. H. Lee, and S. S. Wong, “Distributed ESD protection for high-speed integrated circuits,” IEEE Transactions on Electron Devices, Vol. 21, pp. 390–392, August 2000.
[3] S. Hyvonen, S. Joshi, and E. Rosenbaum, “Cancellation technique to provide ESD protection for multi-GHz RF inputs,” Electronic Letters, Vol. 39, No. 3, pp. 284–286, February 2003.
[4] A. Chatterjee and T. Polgreen, “A low-voltage triggering SCR for on-chip ESD protection at output and input pads,” IEEE Electron Device Letters, Vol. 12, pp. 21–22, August 1991.
[5] E. R. Worley, R. Gupta, B. Jones, R. Kjar, C. Nguyen, and M. Tennyson, “Sub-micron chip ESD protection schemes which avoid avalanching junctions,” in Processing, EOS/ ESD Symposium, pp. 13–20, 1995.
[6] H. Feng, G. Chen, R. Zhan, Q. Wu, X. Guan, H. Xie, and A. Z. H. Wang, “A mixed-mode ESD protection circuit simulation-design methodology,” IEEE Journal Soilid- State Circuits, Vol. 38, pp. 995–1006, June 2003.
[7] B. Fankhauser and B. Deutschmann, “Using device simulations to optimize ESD protection circuits”, in Processing, IEEE EMC Symposium, pp. 963–968, 2004.
[8] ATLAS II Framework, Version 5.10.2.R, Silvaco International, 2005.
[9] A. Amerasekera, L. van Roozendaal, J. Bruines, and F. Kuper, “Characterization and modeling of second breakdown in nMOST’s for extraction and ESD-related process and design parameters,” IEEE Transactions on Electron Devices, Vol. 38, pp. 2161–2168, September 1991.
[10] C. H. Diaz, S. M. Kang, and C. Duvvury, “Modeling of electrical overstress in integrated circuit,” Kluwer Academic Publishers, 1995.
[11] Z. H. Liu, E. Rosenbaum, P. K. Ko, C. Hu, Y. C. Cheng, C. G. Sodini, B. J. Gross, and T. P. Ma, “A comparative study of the effect of dynamic stressing on high-field endurance and stability of reoxidized-nitrided, fluorinated and conventional oxides,” in IEDM Technology Digest, pp. 723–726, 1991.
[12] G. Chen, H. Fang, and A. Wang, “A systematic study of ESD protection structures for RF ICs,” in Processing, IEEE Radio Frequency Integrated Circuit Symposium, Vol. 46, pp. 347–350, 2003.
[13] J. Y. Choi, “AC modeling of the ggNMOS ESD protection device,” ETRI Journal, Vol. 27, No. 5, pp. 628–634, October 2005.

Copyright © 2024 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.