Neural Network Based on SET Inverter Structures: Neuro-Inspired Memory

Abstract

This paper presents a basic block for building large-scale single-electron neural networks. This macro block is completely composed of SET inverter circuits. We present and discuss the basic parts of this device. The full design and simulation results were done using MATLAB and SIMON, which are a single-electron tunnel device and circuit simulator based on a Monte Carlo method. Special measures had to be taken in order to simulate this circuit correctly in SIMON and compare results with those of SPICE simulation done before. Moreover, we study part of the network as a memory cell with the idea of combining the extremely low-power properties of the SET and the compact design.

Share and Cite:

Hafsi, B. , Elmissaoui, R. and Kalboussi, A. (2014) Neural Network Based on SET Inverter Structures: Neuro-Inspired Memory. World Journal of Nano Science and Engineering, 4, 134-142. doi: 10.4236/wjnse.2014.44017.

Conflicts of Interest

The authors declare no conflicts of interest.

References

[1] Beaumont, A. (2009) Room Temperature Single-Electron Transistor Featuring Gate-Enhanced On-State Current. IEEE Electron Device Letters, 31, 249.
[2] Mandal, S. (2013) Single Electron Transistor. International Journal of Innovations in Engineering and Technology (IJIET), 2.
[3] Van de Haar, R., et al. (2003) Simulation of a Neural Node Using SET Technology. Springer-Verlag, Berlin, Heidelberg, 377-386.
[4] Guo, L., Leobandung, E. and Chou, S.Y. (1997) A Silicon Single Electron Transistor Memory Operating at Room Temperature. Science, 275, 649-651.
http://dx.doi.org/10.1126/science.275.5300.649
[5] Wasshuber, C. (1998) SIMON2.0. Institute for Micro Electronics, TU, Vienna.
[6] MATLAB R2009b.http://www.mathworks.com
[7] Scholze, A. (2000) Simulation of Single-Electron Devices. Ph.D. Thesis, Swiss Federal Institute of Technology, Zurich.
[8] Paulthurai, A. and Dharmaraj, B. (2012) Single Electron 2-Bits Multiplier. International Journal of Computer Applications, 42, 17-20.
http://dx.doi.org/10.5120/5680-7719
[9] Boubaker, A., Krout, I. and Kalboussi, A. (2011) Study and Modelling Hybrid MTJ/Ring Memory Using Simon Simulator.
[10] Nakazato, K. and Ahmed, A. (1995) The Multiple-Tunnel Junction and Its Application to Single-Electron Memory and Logic Circuits. Japanese Journal of Applied Physics, 34, 700-706.
http://dx.doi.org/10.1143/JJAP.34.700
[11] Hafsi, B., Boubaker, A., Krout, I. and Kalboussi, A. (2013) Simulation of Single Electron Transistor Inverter Neuron: Memory Application. International Journal of Information and Computer Sciences (IJICS), 2, 8-15.
[12] Bajpai, S., Jain, K. and Jain, N. (2011) Artificial Neural Networks. International Journal of Soft Computing and Engineering (IJSCE), 1, 28.
[13] Gürcan, O., Bernon, C. and Türker, K.S. (2012) Towards a Self-Organized Agent-Based Simulation Model for Exploration of Human Synaptic Connections. arXiv:1207.3760.
[14] Kuzum, D., Jeyasingh, R.G.D., Lee, B. and Philip Wong, H.S. (2011) Nanoelectronic Programmable Synapses Based on Phase Change Materials for Brain-Inspired Computing. Nano Letters, 12, 2179-2186.
[15] Rosenblatt, F. (1962) Principles of Neurodynamics: Perceptrons and the Theory of Brain Mechanisms. Spartan, New York.
[16] McCulloch, W.S. and Pitts, W.H. (1943) A Logical Calculus of the Ideas Immanent in Nervous Activity. Bulletin of Mathematical Biophysics, 5, 115-133.
http://dx.doi.org/10.1007/BF02478259
[17] Van de Haar, R. (2004) Simulation of Single-Electron Tunnelling Circuits Using SPICE. Ph.D. Dissertation, Delft University of Technology, Delft.
[18] Van de Haar, R. and Hoekstra, J. (2003) Simulation of a Neural Node Using SET Technology. Proceeding ICES’03, Proceedings of the 5th International Conference on Evolvable System: From Biology to Hardware, Springer-Verlag, Berlin, Heidelberg, 377-386.
[19] Boubaker, A., Sghaier, N., Souifi, A. and Kalboussi, A. (2010) Simulation and Modeling of the Write/Erase Kinetics and the Retention Time of Single Electron Memory at Room Temperature. Journal of Semiconductor Technology and Science, 10, 143-151.

Copyright © 2023 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.