Fault Tolerance Limits and Input Stimulus Selection Using an Implemented FPGA-Based Testing System

DOI: 10.4236/jcc.2014.213003   PDF   HTML     2,248 Downloads   2,617 Views  


In this paper, the selection of fault tolerance limits and input stimulus using an implemented adaptive FPGA-based testing system based on a method utilizing wavelet transformation of the current waveforms is presented. The testing scheme is innovative because it offers the ability of applying different input stimulus signals with respect to the requirements of the examined circuit. Moreover, the method used is simple, offers a single-point test measurement solution and may easily be adapted to test various other analog and mixed-signal systems. Experimental results are presented showing the advantages of the proposed testing scheme.

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Dimitrios, P. , Sotirios, P. and Vassilios, V. (2014) Fault Tolerance Limits and Input Stimulus Selection Using an Implemented FPGA-Based Testing System. Journal of Computer and Communications, 2, 18-24. doi: 10.4236/jcc.2014.213003.

Conflicts of Interest

The authors declare no conflicts of interest.


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