FPGA Simulation of Linear and Nonlinear Support Vector Machine
Davood Mahmoodi, Ali Soleimani, Hossein Khosravi, Mehdi Taghizadeh
DOI: 10.4236/jsea.2011.45036   PDF   HTML     6,389 Downloads   12,024 Views   Citations


Simple hardware architecture for implementation of pairwise Support Vector Machine (SVM) classifiers on FPGA is presented. Training phase of the SVM is performed offline, and the extracted parameters used to implement testing phase of the SVM on the hardware. In the architecture, vector multiplication operation and classification of pairwise classifiers is designed in parallel and simultaneously. In order to realization, a dataset of Persian handwritten digits in three different classes is used for training and testing of SVM. Graphically simulator, System Generator, has been used to simulate the desired hardware design. Implementation of linear and nonlinear SVM classifier using simple blocks and functions, no limitation in the number of samples, generalized to multiple simultaneous pairwise classifiers, no complexity in hardware design, and simplicity of blocks and functions used in the design are view of the obvious characteristics of this research. According to simulation results, maximum frequency of 202.840 MHz in linear classification, and classification accuracy of 98.67% in nonlinear one has been achieved, which shows outstanding performance of the hardware designed architecture.

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D. Mahmoodi, A. Soleimani, H. Khosravi and M. Taghizadeh, "FPGA Simulation of Linear and Nonlinear Support Vector Machine," Journal of Software Engineering and Applications, Vol. 4 No. 5, 2011, pp. 320-328. doi: 10.4236/jsea.2011.45036.

Conflicts of Interest

The authors declare no conflicts of interest.


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