A 1-GHz, 7-mW, 8-Bit Subranging ADC without Resistor Ladder Using Built-In Threshold Calibration

DOI: 10.4236/cs.2014.54010   PDF   HTML     4,183 Downloads   5,961 Views   Citations

Abstract

A subranging analog-to-digital converter (ADC) features high-speed and relatively low-power. The limiting factors of power reduction in subranging ADCs are the resistor ladder and the comparator. We propose an ADC architecture combining a capacitive digital-to-analog convertor and built-in threshold calibration to eliminate the resistor ladder, resulting in a low-power subranging ADC. We also propose a calibration technique comprising of metal-oxide-metal capacitor, MOS switch, and scaling capacitor to reduce the power consumption of the comparator and an offset drift compensation technique to enable precise foreground calibration. We designed an 8-bit, 1-GHz subranging ADC by applying these techniques, and post-layout simulation results demonstrated a power consumption of 7 mW and figure of merit of 51 fJ/conv.-step.

Share and Cite:

Ohhata, K. , Yoshimura, W. , Tabira, D. , Shimozono, F. and Iwamoto, M. (2014) A 1-GHz, 7-mW, 8-Bit Subranging ADC without Resistor Ladder Using Built-In Threshold Calibration. Circuits and Systems, 5, 76-88. doi: 10.4236/cs.2014.54010.

Conflicts of Interest

The authors declare no conflicts of interest.

References

[1] Yun-Shiang, S. (2012) A 6b 3GS/s 11 mW Fully Dynamic Flash ADC in 40 nm CMOS with Reduced Number of Comparators. 2012 Symposium on VLSI Circuits (VLSIC), 2012, 26-27.
[2] Nakajima, Y., Kato, N., Sakaguchi, A., Ohkido, T., Shimomaki, K., Masuda, H., et al. (2012) A 7b 1.4GS/s ADC with Offset Drift Suppression Techniques for One-Time Calibration. 2012 IEEE Custom Integrated Circuits Conference (CICC), 2012, 1-4.
[3] Jong-In, K., Wan, K., Barosaim, S. and Seung-Tak, R. (2011) A Time-Domain Latch Interpolation Technique for Low Power Flash ADCs. 2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, 1-4.
[4] Ohhata, K., Takase, H., Tateno, M., Arita, M., Imakake, N. and Yonemitsu, Y. (2012) A 1-GHz, 17.5-mW, 8-Bit Subranging ADC Using Offset-Cancelling Charge-Steering Amplifier. 2012 IEEE Asian Solid State Circuits Conference (A-SSCC), 2012, 149-152.
[5] Ku, I.N., Xu, Z., Yen-Cheng, K., Yen-Hsiang, W. and Chang, M.C.F. (2011) A 40-mW 7-Bit 2.2-GS/s Time-Interleaved Subranging ADC for Low-Power Gigabit Wireless Communications in 65-nm CMOS. 2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, 1-4.
[6] Yung-Hui, C. and Jieh-Tsorng, W. (2011) A 16-mW 8-Bit 1-GS/s Subranging ADC in 55nm CMOS. 2011 Symposium on VLSI Circuits (VLSIC), 2011, 128-129.
[7] Ohhata, K., Uchino, K., Shimizu, Y., Oyama, Y. and Yamashita, K. (2008) A 770-MHz, 70-mW, 8-Bit Subranging ADC Using Reference Voltage Precharging Architecture. Solid-State Circuits Conference, 2008. A-SSCC’08. IEEE Asian, 2008, 41-44.
[8] Yuan-Ching, L. (2012) A 4.5-mW 8-b 750-MS/s 2-b/Step Asynchronous Subranged SAR ADC in 28-nm CMOS Technology. 2012 Symposium on VLSI Circuits (VLSIC), 2012, 88-89.
[9] Chi-Hang, C., Yan, Z., Sai-Weng, S., Seng-Pan, U. and Martins, R.P. (2012) A 3.8 mW 8b 1GS/s 2b/Cycle Interleaving SAR ADC with Compact DAC Structure. 2012 Symposium on VLSI Circuits (VLSIC), 2012, 86-87.
[10] Stepanovic, D. and Nikolic, B. (2012) A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS. 2012 Symposium on VLSI Circuits (VLSIC), 2012, 84-85.
[11] Doris, K., Janssen, E., Nani, C., Zanikopoulos, A. and Van Der Weide, G. (2011) A 480 mW 2.6 GS/s 10b 65 nm CMOS Time-Interleaved ADC with 48.5 dB SNDR up to Nyquist. 2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011, 180-182.
[12] Zhiheng, C. and Shouli, Y. (2008) A 52 mW 10b 210 MS/s Two-Step ADC for Digital-IF Receivers in 0.13μm CMOS. Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE, 2008, 309-312.
[13] Asada, Y., Yoshihara, K., Urano, T., Miyahara, M. and Matsuzawa, A. (2009) A 6 Bit, 7 mW, 250 fJ, 700 MS/s Subranging ADC. Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian, 2009, 141-144.
[14] Van der Plas, G., Decoutere, S. and Donnay, S. (2006) A 0.16 pJ/Conversion-Step 2.5 mW 1.25 GS/s 4b ADC in a 90 nm Digital CMOS Process. Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International, 2006, 2310.
[15] Tsugaru, K., Sugimoto, Y., Noda, M., Iwai, H., Sasaki, G. and Suwa, Y. (1989) A 10 bit 40 MHz ADC Using 0.8 μm Bi-CMOS Technology. Bipolar Circuits and Technology Meeting, 1989, Proceedings of the 1989, 1989, 4851.
[16] Lee, H., Asada, Y., Miyahara, M. and Matsuzawa, A. (2013) A 6 Bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation. IEICE Transaction on Fundamentals, E96-A, 422-433.
[17] Figueiredo, P.M., Cardoso, P., Lopes, A., Fachada, C., Hamanishi, N., Tanabe, K., et al. (2006) A 90 nm CMOS 1.2v 6b 1GS/s Two-Step Subranging ADC. Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International, 2006, 2320-2329.
[18] Jong-In, K., Ba-Ro-Saim, S., Wan, K. and Seung-Tak, R. (2013) A 6-b 4.1-GS/s Flash ADC with Time-Domain Latch Interpolation in 90-nm CMOS. IEEE Journal of Solid-State Circuits, 48, 1429-1441.
[19] Paik, D., Miyahara, M. and Matsuzawa, A. (2012) An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E95-A, 456-470.
[20] Kull, L., Toifl, T., Schmatz, M., Francese, P.A., Menolfi, C., Braendli, M., et al. (2013) A 3.1 mW 8b 1.2 GS/s SingleChannel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS. 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013, 468-469.
[21] Chiang, S.H.W., Hyuk, S. and Razavi, B. (2013) A 10-Bit 800-MHz 19-mW CMOS ADC. 2013 Symposium on VLSI Circuits (VLSIC), 2013, C100-C101.

  
comments powered by Disqus

Copyright © 2020 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.