Study on Test Compaction in High-Level Automatic Test Pattern Generation (ATPG) Platform


Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic test pattern generation (ATPG). In addition, ATPG needs to deal with new defects caused by process variation when IC is shrinking. To reduce the computation effort of ATPG, test generation could be started earlier at higher abstraction level, which is in line with top-down design methodology that has become more popular nowadays. In this research, we employ Chen’s high-level fault model in the high-level ATPG. Besides shorter ATPG time as shown in many previous works, our study showed that high-level ATPG also contributes to test compaction. This is because most of the high-level faults correlate with the gate-level collapsed faults especially at input/output of the modules in a circuit. The high-level ATPG prototype used in our work is mainly composed by constraint-driven test generation engine and fault simulation engine. Experimental result showed that more reduced/compact test set can be generated from the high-level ATPG.

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A. Abdullah and C. Ooi, "Study on Test Compaction in High-Level Automatic Test Pattern Generation (ATPG) Platform," Circuits and Systems, Vol. 4 No. 4, 2013, pp. 342-349. doi: 10.4236/cs.2013.44046.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] B. L. Michael and A. D. Vishwani, “Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits,” Kluwer Academic Publishers, New York, 2002.
[2] H. C. Chien-In, “Behavioral Test Generation/Fault Simu lation,” IEEE Potentials, Vol. 22, No. 1, 2003, pp. 27-32. doi:10.1109/MP.2003.1180938
[3] G. D. Giuseppe, F. Franco, et al., “Test Generation Based on CLP,” 8th International Workshop on Micro processor Test and Verification, Common Challenges and Solutions, Austin, 5-6 December 2009, pp. 98-105.
[4] D. G. Guglielmo, F. Fummi, C. Marconcini and G. Pra vadelli, “Improving High-Level and Gate-Level Testing with FATE: A Functional Automatic Test Pattern Gen erator Traversing Unstabilised Extended FSM,” IET Computers & Digital Techniques, Vol. 1, No. 3, 2007, pp. 187-196. doi:10.1049/iet-cdt:20060139
[5] Y. Sun, “Automatic Behavioral Test Generation by Using a Constraint Solver,” Master’s Thesis, Linkoping University, Linkoping, 2001.
[6] S. Brand, “Sequential Automatic Test Pattern Generation by Constraint Programming,” Proceedings of CP 2001 Workshop on Modelling and Problem Formulation, Cy prus, 1 December 2001, pp. 1-8.
[7] S. D. Hochbaum, “An Optimal Test Compression Proce dure for Combinational Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Sys tems, Vol. 15, No. 10, 1996, pp. 1294-1299.
[8] N. Zainalabedin, “Digital System Test and Testable De sign Using HDL Models and Architectures,” Springer, New York, 2011.
[9] R. Guo, S. M. Reddy, et al., “Reverse-Order-Restora tion-Based Static Test Compaction for Synchronous Sequential Circuits,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 22, No. 3, 2003, pp. 293-304.
[10] M. S. Hsiao, E. M. Rudnick and J. H. Patel, “Sequential Circuit Test Generation Using Dynamic State Traversal,” Proceedings of the 1997 European Design and Test Con ference, Paris, 17-20 March 1997, pp. 22-28.
[11] W. Snyder, “Verilator-3.810,” Veripool, 2010.
[12] F. Corno, S. M. Reorda and G., Squillero, “RT-Level ITC‘99 Benchmarks and First ATPG Results,” IEEE De sign & Test of Computers, Vol. 17, No. 3, 2000, pp. 44-53. doi:10.1109/54.867894.

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