Design of a CMOS Optical Receiver Front-End Using 0.18 μm Technology


This paper reports design of a CMOS optical receiver front-end using 0.18 μm technology. Design process is current associated with photodiode using trans-impedance amplifier (TIA) for wide bandwidth, high gain, low input referred noise and wide dynamic range. The Automated Gain Control (AGC) voltage is used to provide variable gain for multilevel signals. This design is simulated in 0.18 μm UMC technology for the performance analysis. The best simulation results are reported the maximum TIA gain of 67.26 dB? at 0 V AGC followed by a post amplifier gain of 86.70 dB?. The bandwidth range is 7.03 GHz to 11.5 GHz corresponding to 0 - 3 V AGC respectively. The input referred noise level value is 43.86 pA/√Hz up to 10 GHz frequency. In addition authors have obtained the common mode rejection ratio (CMRR) is 72.42 dB and rectified group delay is 144.48 ps. Verification of the design, reported results are compared with earlier published work and improvements obtained in the present results.

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A. Shukla, R. Gamad and R. Raikwar, "Design of a CMOS Optical Receiver Front-End Using 0.18 μm Technology," Wireless Engineering and Technology, Vol. 4 No. 1, 2013, pp. 46-53. doi: 10.4236/wet.2013.41007.

Conflicts of Interest

The authors declare no conflicts of interest.


[1] R. D. Bespalko, “Transimpedance Amplifier Design Using 0.18 μm CMOS Technology,” Queen’s University Kingston, Ontario, 2007.
[2] R. Y. Chen, T. S. Hung and C. Y. Hung, “A CMOS Infrared Wireless Optical Receiver Front-End with a Variable-Gain Fully-Differential Transimpedance Amplifier,” IEEE Transactions on Consumer Electronics, Vol. 51, No. 2, 2005, pp. 424-429. doi:10.1109/TCE.2005.1467982
[3] S. Hranilovic and D. A. Johns, “A Multilevel Modulation Scheme for High-Speed Wireless Infrared Communications,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 6, 1999, pp. 338-341.
[4] D. Guckenberger, J. Schaub and K. Komegay, “A DC Coupled Low-Power Transimpedance Amplifier Architecture for Gb/s Communication System Applications,” Design of Radio Frequency Integrated Circuit (RFIC) Symposium, June 2004, pp. 515-518.
[5] B. Razavi, “Design of Integrated Circuits for Optical Communications,” McGraw Hill, Boston, 2003.
[6] C. Ciofietal, “A New-Circuit Topology for the Realization of Very Low-Noise Wide-Bandwidth Trans-Impedance Amplifier,” IEEE Transactions on Instrument and Measurement, Vol. 56, No. 5, 2007 pp. 1626-1631.
[7] A. S. Sedra and K. C. Smith, “Microelectronic Circuits,” 4th Edition, Oxford University Press, New York, 1998.
[8] A. Phillip and D. R. Holberg, “CMOS Analog Circuit Design,” 2nd Edition, Oxford University Press, New York, 2003.
[9] F. T. Chien and Y. J. Chan, “Bandwidth Enhancement of Transimpedance Amplifier by a Capacitive Peaking Design,” IEEE Journal of Solid State Circuits, Vol. 34, 1999, pp. 1167-1170.
[10] S. M. Park and H.-J. Yoo, “1.25-Gb/s Regulated Cascade CMOS Transimpedance Amplifier for Gigabit Ethernet Applications,” IEEE Journal of Solid State Circuits, Vol. 39, No. 1, 2004, pp. 112-121. doi:10.1109/JSSC.2003.820884

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