New Hybrid Digital Circuit Design Techniques for Reducing Subthreshold Leakage Power in Standby Mode

Manish Kumar, Md. Anwar Hussain, Sajal K. Paul

Department of ECE, North Eastern Regional Institute of Science & Technology, Nirjuli, Arunachal Pradesh, India.
Department of Electronics Engineering, Indian School of Mines, Dhanbad, Jharkhand, India.

DOI: 10.4236/cs.2013.41012                

Abstract

In this paper, four new hybrid digital circuit design techniques, namely, hybrid multi-threshold CMOS complete stack technique, hybrid multi-threshold CMOS partial stack technique, hybrid super cutoff complete stack technique and hybrid super cutoff partial stack technique, have been proposed to reduce the subthreshold leakage power dissipation in standby modes. Techniques available in literature are compared with our proposed hybrid circuit design techniques. Performance parameters such as subthreshold leakage power dissipation in active and standby modes, dynamic power dissipation and propagation delay, are compared using existing and proposed hybrid techniques for a two input AND gate. Reduction of subthreshold leakage power dissipation in standby mode is given more importance, in comparison with the other circuit design performance parameters. It is found that there is reduction in subthreshold leakage power dissipation in standby and active modes by 3.5× and 1.15× respectively using the proposed hybrid super cutoff complete stack technique as compared to the existing multi-threshold CMOS (MTCMOS) technique. Also a saving of 2.50× and 1.04× in subthreshold leakage power dissipation in standby and active modes respectively were observed using hybrid super cutoff complete stack technique as compared to the existing super cutoff CMOS (SCCMOS) technique. The proposed hybrid super cutoff stack technique proved to perform better in terms of subthreshold leakage power dissipation in standby mode in comparison with other techniques. Simulation results using Microwind EDA tool in 65 nm CMOS technology is provided in this paper.

Keywords

Subthreshold Leakage Power; Standby Mode; Active Mode; Propagation Delay

Conflicts of Interest

The authors declare no conflicts of interest.

References

[1]	J. Rabaey, “Low Power Design Essentials: Integrated Circuits and Systems,” Springer-Verlag, Berlin, 2009. doi:10.1007/978-0-387-71713-5
[2]	S. Dasgupta, A. A. P. Sarab and D. Datta, “Nanoscale Device Architecture to Reduce Leakage Current through Quantum-Mechanical Simulation,” Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, Vol. 24, No. 3, 1906, pp. 1384-1397. doi:10.1116/1.2201040
[3]	M. Kumar, Md. A. Hussain and S. K. Paul, “Performance of a Two Input Nand Gate Using Subthreshold Leakage Control Techniques,” Journal of Electron Devices, Vol. 14, 2012, pp. 1161-1169.
[4]	M. Kumar, Md. A. Hussain and L. K. Singh, “Design of a Low Power High Speed ALU in 45 nm Using GDI Technique and Its Performance Comparison,” Communications in Computer and Information Science, Vol. 142, 2011, pp. 458-463. doi:10.1007/978-3-642-19542-6_87
[5]	M. Kumar, “Realization of a Low Power High Performance IC Design Technique for Wireless Portable Communication Devices Used in Underground Mines,” Special Issues on IP Multimedia Communications (1), International Journal of Computer Application, 2011, pp. 52-54.
[6]	S. Borkar, “Design Challenges of Technology Scaling,” IEEE Micro, Vol. 19, No. 4, 1999, pp. 23-29. doi:10.1109/40.782564
[7]	A. Keshavarzi, K. Roy and C. Hawkins, “Intrinsic Leakage in Low Power Deep Submicron CMOS ICs,” Proceedings of the International Test Conference, Washington DC, 1-6 November 1997, pp. 146-155.
[8]	S. Mutoh, T. Douseki, Y. Matsuya, et al., “1 V Power Supply High-Speed Digital Circuit Technology with Multithreshold Voltage CMOS,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 8, 1995, pp. 847-854. doi:10.1109/4.400426
[9]	M. Anis, S. Areibi and M. Elmasry, “Design and Optimization of Multi-Threshold CMOS (MTCMOS) Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 10, 2003, pp. 1324-1342. doi:10.1109/TCAD.2003.818127
[10]	H. Kawaguchi, K. Nose and T. Sakurai, “A Super Cutoff CMOS (SCCMOS) Scheme for 0.5 V Supply Voltage with Picoampere Standby Current,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 10, 2000, pp. 1498-1501. doi:10.1109/4.871328
[11]	M. Johnson, D. Somasekhar, L. Y. Chiou and K. Roy, “Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 10, No. 1, 2002, pp. 1-5. doi:10.1109/92.988724
[12]	T. G. Reddy and K. Suganthi, “Super Stack Technique to Reduce Leakage Power for Sub 0.5 V Supply Voltage in VLSI Circuits,” Proceedings of International Conference on Sustainable Energy and Intelligent Systems, Chennai, 20-22 July 2011, pp. 585-588.
[13]	V. Neema, S. S. Chouhan and S. Tokekar, “Novel Circuit Technique for Reduction of Active Drain Current in Series/Parallel PMOS Transistors Stack,” Proceedings of International Conference on Electronic Devices, Systems and Applications, Kuala Lumpur, 11-14 April 2010, pp. 368-372. doi:10.1109/ICEDSA.2010.5503038
[14]	J. C. Park and V. J. Mooney, “Sleepy Stack Leakage Reduction,” IEEE Transactions on Very Large Scale Integration Systems , Vol. 14, No. 11, 2006, pp. 1250-1263. doi:10.1109/TVLSI.2006.886398
[15]	K. Roy, S. Mukhopadhyay and H. M. Meimand, “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits,” Proceedings of the IEEE, Vol. 91, No. 2, 2003, pp.305-327. doi:10.1109/JPROC.2002.808156
[16]	A. Chandrakasan, W. J. Bowhill and F. Fox, “Design of High-Performance Microprocessor Circuits,” IEEE Press, New York, 2001.
[17]	B. J. Sheu, D. L. Scharfetter, P. K. Ko and M. C. Jeng, “BSIM: Berkeley Short Channel IGFET Model For MOS Transistors,” IEEE Journal of Solid-State Circuits, Vol. 22, No. 4, 1987, pp. 558-566. doi:10.1109/JSSC.1987.1052773
[18]	M. Anis and M. Elmasry, “Multi-Threshold CMOS Digital Circuits: Managing Leakage Power,” Kluwer Academic Publishers, Norwell, 2010.
[19]	B. S. Deepaksubramanyan and Adrian Nunez, “Analysis of Subthreshold Leakage Reduction in CMOS Digital Circuits,” Proceedings of the 13th NASA VLSI Symposium, Idaho, 5-8 August 2007, pp. 1-8.
[20]	N. S. Kim, Ann Arbor, T. Austin, et al., “Leakage Current: Moore’s Law Meets Static Power,” IEEE Computer, Vol. 36, No. 12, 2003, pp. 68-75. doi:10.1109/MC.2003.1250885