[1]
|
T. Komuro, S. Kagami, and M. Ishikawa, “A Dynami-cally Reconfigurable SIMD Processor for a Vision Chip,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 1, 2004. doi: 10.1109/JSSC.2003.820876
|
[2]
|
W .C. Zhang, Q. Y. Fu, and N. J. Wu, “ A Programmable Vision Chip Based on Multiple Levels of Parallel Processors,” IEEE Journal of Solid-State Circuits, Vol. 46, No. 9, 2011. doi: 10.1109/JSSC.2011.2158024
|
[3]
|
J. Hennessy, D.A. Pat-terson, “Computer Architecture: A Quantitative Ap-proach,” 5th Edition, Morgan Kaufmann, San Francisco, CA, 2011.
|