Design of DC-DC Converter for Flash Memory IPs ()
Li-yan Jin,
Woo-Young Jung,
Ji-Hye Jang,
Min-Sung Kim,
Myeong-Seok Kim,
Heon Park,
Pan-Bong Ha,
Young-Hee Kim
Department of electronic engineering, Chanwon National University, Changwon , South Korea.
DOI: 10.4236/eng.2013.51B026
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Abstract
A DC-DC converter for flash memory IPs performing erasing by the FN (Fowler-Nordheim) tunneling and programming by the CHEI (channel hot electron injection) is designed in this paper. For the DC-DC converter for flash memory IPs using a dual voltage of VDD (=1.5V±0.15V)/VRD (=3.1V±0.1V), a scheme of using VRD (Read Voltage) instead of VDD is proposed to reduce the pumping stages and pumping capacitances of its charge pump circuit. VRD (=3.1V±0.1V) is a regulated voltage by a voltage regulator with an external voltage of 5V, which is used as the WL activation voltage in the read mode and an input voltage of the charge pump. The designed DC-DC converter outputs positive voltages of VP6V (=6V), VP8V (=8V) and VP9V(=9V); and a negative voltage of VM8V (=-8V) in the write mode.
Share and Cite:
L. Jin, W. Jung, J. Jang, M. Kim, M. Kim, H. Park, P. Ha and Y. Kim, "Design of DC-DC Converter for Flash Memory IPs,"
Engineering, Vol. 5 No. 1B, 2013, pp. 142-145. doi:
10.4236/eng.2013.51B026.
Conflicts of Interest
The authors declare no conflicts of interest.
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