Share This Article:

A Simple On-Chip Automatic Tuning Circuit for Continuous-Time Filter

Abstract Full-Text HTML Download Download as PDF (Size:975KB) PP. 66-71
DOI: 10.4236/ijcns.2010.31009    6,037 Downloads   11,311 Views  

ABSTRACT

A simple on-chip automatic frequency tuning circuit is proposed. The tuning circuit is modified from voltage-controlled filter (VCF) frequency tuning circuit. We utilize an operational transconductance amplifier and a capacitor to from a single-time constant (STC) circuit which can produce a controllable delay time clock to tune the frequency of the filter. It can efficiently reduce the deviations in the 3 dB bandwidth from the variations of PVT (Process, Voltage and Temperature). The design of the STC circuit is simpler than VCF and it has less chip area. The chip has been implanted using TCMC 0.35 μm CMOS technology and the power consumption is less than 9.05 mW.

Conflicts of Interest

The authors declare no conflicts of interest.

Cite this paper

C. KAO, P. TSAI and I. CHANG, "A Simple On-Chip Automatic Tuning Circuit for Continuous-Time Filter," International Journal of Communications, Network and System Sciences, Vol. 3 No. 1, 2010, pp. 66-71. doi: 10.4236/ijcns.2010.31009.

References

[1] Y. P. Tsividis, “Integrated continuous-time filter design - an overview,” IEEE Journal Solid-State Circuits, Vol. 29, No. 3, pp. 166–176, March 1994.
[2] M. Abo and P. R. Gray, “A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter,” IEEE Journal Solid- State Circuits, Vol. 34, No. 5, pp. 599–606, May 1999.
[3] L. Maurer, W. Schelmbauer, H. Pretl, B. Adler, A. Springer, and R. Weigel, “On the design of a continuous-time channel select filter for aZero-IF UMTS receiver,” IEEE Conference Vehicular Technology, Vol. 1, pp. 650–654, May 2000.
[4] M. Durham, W. Redman-White, and J. B. Hughes, “High-linearity continuous-time filter in 5-V VLSI CMOS,” IEEE Journal Solid-State Circuits, Vol. 27, No. 9, pp. 1270–1276, September 1992.
[5] J. Silva-Martinez, M. S. J. Steyaert, and W. Sansen, “A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chip automatic tuning,” IEEE Journal Solid-State Circuits, Vol. 27, No. 12, pp. 1843–1853, December 1992.
[6] T. H. Teo, E.-S. Khoo, and D. Uday, “Fifth order low-pass transitional Gm-C filter with relaxation oscillator frequency tuning circuit,” IEEE Conference Electron Devices and Solid-State Circuits, pp. 229–232, December 2003.
[7] D. Johns and K. Martin, “Analog integrated circuit design,” John Wiley & Sons on Canada, 1997.
[8] S. Szczepanski and S. Koziel, “A 3.3 V linear fully balanced CMOS operational transconductance amplifier for high-frequency applications,” IEEE Conference Circuits and Systems for Communications, pp. 38–41, June 2002.
[9] H. Traff, “Novel approach to high speed CMOS current comparators,” Electronics Letters, Vol. 28, No. 3, pp. 310–312, January 1992.
[10] H. T. Bui, A. K. Al-Sheraidah, Y. K. Wang, “New 4-transistor XOR and XNOR designs,” IEEE Asia Pacific Conference ASICs, pp. 25–28, August 2000.
[11] W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops,” IEEE International Symposium Circuits and Systems, Vol. 2, pp. 545–548, June 1999.
[12] K. Su, “Analog filters,” Second Edition, Kluwer Academic Publishers, 2001.
[13] Y. P. Tsividis, “Design considerations for high-frequency continuous-time filters and implementation of an antialiasing filter for digital video,” IEEE Journal Solid- State Circuits, Vol. 25, No. 6, pp. 1368–1378, December 1990.
[14] V. Agarwal and S. Sonkusale, “A PVT independent subthreshold Constant-Gm stage for very low frequency applications,” IEEE International Symposium Circuits and Systems, pp. 2909–2912, May 2008.

  
comments powered by Disqus

Copyright © 2019 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.