VLSI Implementation for Low Noise Power Efficiency Cellular Communication Systems

Rondia MACK; Maher RIZKALLA; Paul SALAMA; Mohamed EL-SHARKAWY

doi:10.4236/wsn.2010.21003

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Wireless Sensor Network > Vol.2 No.1, January 2010

VLSI Implementation for Low Noise Power Efficiency Cellular Communication Systems ()

Rondia MACK, Maher RIZKALLA, Paul SALAMA, Mohamed EL-SHARKAWY

DOI: 10.4236/wsn.2010.21003 PDF HTML 5,422 Downloads 9,898 Views

Abstract

A low power model for Code Division Multiple Access (CDMA) based cellular communication system is developed. The dynamic power is minimized by reducing the frequency of the Phase Lock Loop (PLL) after lock is established. The paper addresses the feasibility of lowering the clock frequency of the processing unit that models the PLL is addressed and modulator/demodulator functions of the system while maintaining synchronization with the memory unit and other peripherals. The system is simulated with Matlab considering various Signal-to-Noise Ratios (SNR). For a given SNR, the minimum frequency required for the PLL to maintain lock is determined. The Matlab file is translated to VHDL code, simulated and synthesized with Mentor tools, and the layout then generated. Mach-Pa 5-V software system from Mentor tools is utilized to estimate the power consumed by the simulated device. A Xilinx file is also generated and downloaded for Field Programmable Gate Arrays (FPGA) implementation. A 50 MHz clock frequency of the processing unit was first considered and then lowered to 20 MHz for the low power study. Lowering the base and clock frequency resulted in near 30% reduction in power.

Keywords

Cellular Communication, CDMA, PLL, Harware, Xilinx, Matlab, Low Power

Share and Cite:

R. MACK, M. RIZKALLA, P. SALAMA and M. EL-SHARKAWY, "VLSI Implementation for Low Noise Power Efficiency Cellular Communication Systems," Wireless Sensor Network, Vol. 2 No. 1, 2010, pp. 18-30. doi: 10.4236/wsn.2010.21003.

Conflicts of Interest

The authors declare no conflicts of interest.

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