Hardware/Compiler Memory Protection in Sensor Nodes

DOI: 10.4236/ijcns.2008.13028   PDF   HTML     5,611 Downloads   9,332 Views   Citations

Abstract

With reference to sensor node architectures, we consider the problem of supporting forms of memory protection through a hardware/compiler approach that takes advantage of a low-cost protection circuitry inside the microcontroller, interposed between the processor and the storage devices. Our design effort complies with the stringent limitations existing in these architectures in terms of hardware complexity, available storage and energy consumption. Rather that precluding deliberately harmful programs from producing their effects, our solution is aimed at limiting the spread of programming errors outside the memory scope of the running program. The discussion evaluates the resulting protection environment from a number of salient viewpoints that include the implementation of common protection paradigms, efficiency in the distribution and revocation of access privileges, and the lack of a privileged (kernel) mode.

Share and Cite:

L. LOPRIORE, "Hardware/Compiler Memory Protection in Sensor Nodes," International Journal of Communications, Network and System Sciences, Vol. 1 No. 3, 2008, pp. 235-240. doi: 10.4236/ijcns.2008.13028.

Conflicts of Interest

The authors declare no conflicts of interest.

  
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