Author(s)

Patikineti Sreenivasulu^1*, Srinivasa Rao², Vinaya Babu³

¹ECE Department, JNTUK, Andhrapradesh, Kakinada, India.
²ECE Department, TRR College of Engineering, Hyderabad, India.
³CSE Department, JNTUH College of Engineering, Hyderabad, India.

Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). Many power reduction techniques have also been proposed from the system level down to the circuit level. High-speed computation has thus become the expected norm from the average user, instead of being the province of the few with access to a powerful mainframe. Power must be added to the portable unit, even when power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Techniques for low-power operation are shown in this paper, which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. The threshold vol-tages of the MTCMOS devices for both low and high V_th are constructed as the low threshold V_th is approximately 150 - 200 mv whereas the high threshold V_th is managed by varying the thickness of the oxide T_ox. Hence we are using different threshold voltages with minimum voltages and hence considered this project as ultra-low power designing.

Ultra-Low Power Design, Dynamic Power, Static Power, Switching Activities, Leakage Power, Power Optimization

Sreenivasulu, P. , Rao, S. and Babu, V. (2015) Ultra-Low Power Designing for CMOS Sequential Circuits. International Journal of Communications, Network and System Sciences, 8, 146-153. doi: 10.4236/ijcns.2015.85016.