A Process Variation Tolerant OTA Design for Low Power ASIC Design ()
ABSTRACT
Technology development and
continuous down scaling in CMOS fabrication makes Mixed Signal Integrated
Circuits (MSIC) more vulnerable to process variation. This paper presents a
well defined novel design methodology for process variability aware design by incorporating
the major challenge of statistical circuit performance relating the device and
circuit level variation in an accurate and efficient manner to improve the
reliability, robustness and stability of the circuit. The device sensitive
parameters are identified and accurately quantified by continuous realistic
assessments using statistical methods. The modularity of the methodology can be
validated by the output performance obtained from the gain and phase response
of OTA which is highly stable when subjected to worst case process variation
scenario. In the proposed optimization, the circuit is strengthened by fixing
the optimum aspect ratio without adding any additional compensation devices
complicating the circuit resulting in low power consumption of only 0.116 mW in
standard CMOS 0.18 μm technology with 1.8 V power supply.
Share and Cite:
Benschwartz, R. and Sakthivel, P. (2016) A Process Variation Tolerant OTA Design for Low Power ASIC Design.
Circuits and Systems,
7, 956-970. doi:
10.4236/cs.2016.76081.