Circuits and Systems

Volume 5, Issue 7 (July 2014)

ISSN Print: 2153-1285   ISSN Online: 2153-1293

Google-based Impact Factor: 0.48  Citations  

An IEEE 1149.x Embedded Test Coprocessor

HTML  XML Download Download as PDF (Size: 1420KB)  PP. 170-180  
DOI: 10.4236/cs.2014.57019    4,324 Downloads   5,974 Views  Citations

ABSTRACT

This paper describes a microprogrammed architecture for an embedded coprocessor that is able to control IEEE 1149.1 to IEEE 1149.7 test infrastructures, and explains how to expand the supported test command set. The coprocessor uses a fast simplex link (FSL) channel to interface a 32-bit MicroBlaze CPU, but it can work with any microprocessor core that accepts this simple FIFO-based interface method. The implementation cost (logic resource usage for a Xilinx Spartan-6 FPGA) and the performance data (operating frequency) are presented for a test command set comprising two parts: 1) the full IEEE 1149.1 structural test operations; 2) a subset of IEEE 1149.7 operations selected to illustrate the implementation of advanced scan formats.

Share and Cite:

Gebremeskel, U. and Ferreira, J. (2014) An IEEE 1149.x Embedded Test Coprocessor. Circuits and Systems, 5, 170-180. doi: 10.4236/cs.2014.57019.

Cited by

[1] A general boundary scan test system based on EDIF netlist file transfer to Protel netlist file
International Journal of Materials and Structural Integrity, 2016

Copyright © 2024 by authors and Scientific Research Publishing Inc.

Creative Commons License

This work and the related PDF file are licensed under a Creative Commons Attribution 4.0 International License.